An Enhancement to LSSD and Some Applications of LSSD in Reliability, Availability, and Serviceabilit

DasGupta, Sumit; Walther, R.; Williams, T.W.; Eichelberger, E. B.

doi:10.1109/ftcsh.1995.532648

Cited by 74 publications

(22 citation statements)

References 3 publications

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“…This work addresses single path delay faults in a combinational circuit or in an (enhanced) full-scan [18] one, that is composed of functional macros whose implementation is not known.…”

Section: A New Model For Delay Fault Testing In Macro Based Icsmentioning

confidence: 99%

A SAT Based Test Generation Method for Delay Fault Testing of Macro Based Circuits

Mele

Favalli

2011

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…This work addresses single path delay faults in a combinational circuit or in an (enhanced) full-scan [18] one, that is composed of functional macros whose implementation is not known.…”

Section: A New Model For Delay Fault Testing In Macro Based Icsmentioning

confidence: 99%

A SAT Based Test Generation Method for Delay Fault Testing of Macro Based Circuits

Mele

Favalli

2011

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Scan can be used to apply two-pattern tests that start and end with scan operations [1]- [3]. Tests can also be applied using only the functional mode of operation of the circuit.…”

Section: Introductionmentioning

confidence: 99%

A delay fault model for at-speed fault simulation and test generation

Pomeranz

Reddy

2006

Proceedings of the 2006 IEEE/ACM International Conference on Computer-Aided Design - ICCAD '06

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“…The scan-FFs are modified and HOLD latches [28] are often inserted between the FFs and the combinational logic. The latches insert excess delays in the path and increase area overhead due to routing of an additional control (HOLD) signal.…”

Section: Delay Testing Using Rasmentioning

confidence: 99%

A random access scan architecture to reduce hardware overhead

Mudlapur

Agrawal

Singh

IEEE International Conference on Test, 2005.

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The concept of Random Access Scan (RAS) where every Flip-Flop is addressed uniquely has been subject to criticism at the very thought. It seems at the first impulse that the cost associated with routing is overwhelming. This argument has shelved the idea for 25 years now. In this paper we propose an architecture that minimizes the signals to the RAS Flip-Flop (FF) and give an estimate of the increase in area due to the increase in gates and increase in routing. Two global signals, scanin and mode control, have been eliminated from the previous RAS designs presented in the literature. For n flip-flops, instead of routing n address wires, one to each FF, we use √ n wires in an xy matrix layout. A unique toggle mechanism is incorporated in the RAS FF that totally eliminates the scanin signal wire and reduces the vector set up to 60% compared to traditional serial scan (SS). The SS induces unnecessary circuit activity during scan and the circuit under test (CUT) dissipates an enormous amount of power. Our design reduces the power dissipation by 99%. The problem of delay testing is highly constrained in SS and the scan-cell is often modified to assist delay testing. Any single input change delay test can be directly applied in our design. Hence all testable paths in the circuit can be effectly tested without constraints. We also propose a multistage scanout system to observe the addressed FF avoiding a slow output bus with very high capacitance.

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An Enhancement to LSSD and Some Applications of LSSD in Reliability, Availability, and Serviceabilit

Cited by 74 publications

References 3 publications

A SAT Based Test Generation Method for Delay Fault Testing of Macro Based Circuits

A SAT Based Test Generation Method for Delay Fault Testing of Macro Based Circuits

A delay fault model for at-speed fault simulation and test generation

A random access scan architecture to reduce hardware overhead

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