2009 Ph.D. Research in Microelectronics and Electronics 2009
DOI: 10.1109/rme.2009.5201298
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An EPC Class-1 Generation-2 baseband processor for passive UHF RFID tag

Abstract: Passive UHF RFID transponders (tags, in short) are mixed-signal Systems-on-Chip (SoCs) for remotely powered communications which must comply with stringent requirements on current consumption. This brief focuses on the design of a backend digital processor for UHF RFID tags targeting the Class-1 Generation-2 EPC Protocol, and proposes different techniques for reducing its power consumption. After code validation with an FPGA, the processor has been synthetised in a 0.35µm CMOS technology process and occupies 7… Show more

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Cited by 2 publications
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“…The lowest clock frequency meeting this requirement is 1.28MHz. From a power dissipation perspective, 1.28MHz seems to be the appropriate master clock frequency, however, the backward link are not satisfied [21]. On the other hand, in order to achieve a low bit error rate, the minimum clock frequency to drive the counter for PIE decoding must be more than 1.6MHz [22].…”
Section: Clock Management and Clock Gatingmentioning
confidence: 99%
“…The lowest clock frequency meeting this requirement is 1.28MHz. From a power dissipation perspective, 1.28MHz seems to be the appropriate master clock frequency, however, the backward link are not satisfied [21]. On the other hand, in order to achieve a low bit error rate, the minimum clock frequency to drive the counter for PIE decoding must be more than 1.6MHz [22].…”
Section: Clock Management and Clock Gatingmentioning
confidence: 99%