An Equation-Based Circuit Model and Its Generation Tool for 3-D IC Power Delivery Networks With an Emphasis on Coupling Effect

Cheng, Chien‐Chuan; Cheng, Tai-Yu; Du, Cheng-Han; Lu, Yi-Chang; Chiou, Yih-Peng; Liu, Sally; Wu, Tzong–Lin

doi:10.1109/tcpmt.2014.2316301

Cited by 12 publications

(4 citation statements)

References 17 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The capacitance C OA can be obtained by Cheng et al. [13].

C_{O A} = 2 W C_{M} + C_{w t w} - \frac{ϵ_{o x} W^{2}}{H_{1}}

where the capacitance between the upper power (ground) wire and bottom ground (power) wire and the wall‐to‐wall capacitance are calculated by

C_{M} = ϵ_{o x} [\frac{1.15 W}{H_{1}} + 2.8 {(\frac{H}{H_{1}})}^{0.222}]

C_{w t w} = 20 ϵ_{O X} (1.1 + 1.6 e^{- \frac{0.6 H}{P - W}}) H_{1} {(\frac{l - W}{l - W + 2 H_{1}})}^{2.4}

…”

Section: Electrical Modelmentioning

confidence: 99%

“…It is evident that the circuit model results agree well with the HFSS simulation results. In general, the parasitic effects between on‐chip grids and TSVs are negligible, and the impedance of the whole 3‐D IC PDN can be obtained by combining the models of on‐chip grids and TSVs [13]. In this way, the PDN impedance of the whole structure shown in Figure 5a can be obtained and compared with the simulated results (see Figure 5a,b).…”

Section: Electrical Modelmentioning

confidence: 99%

“…P is the distance between adjacent P/G wires. The capacitance C OA can be obtained by Cheng et al [13].…”

Section: Electrical Modelmentioning

confidence: 99%

“…However, to guarantee the yield, the holes should be etched uniformly. To date, different TSV array arrangements and decoupling capacitor techniques have been explored to resolve the power integrity issues [9][10][11][12][13][14]. Furthermore, to reduce the burden of on-die decoupling capacitors, an n þ contact surrounding the power TSV was proposed to enhance its parasitic capacitance at high frequencies [15].…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

On the applicability of two‐bit carbon nanotube through‐silicon via for power distribution networks in 3‐D integrated circuits

Zhao

et al. 2020

IET Circuits, Devices & Syst

View full text Add to dashboard Cite

This study investigates the possibility of the carbon nanotube (CNT)‐based through‐silicon vias (TSVs) for improving power integrity of 3‐D integrated circuits (3‐D ICs). The circuit model is developed for 2‐bit CNT TSV and validated through the full‐wave electromagnetic simulator HFSS simulations. The 2‐bit CNT TSV is applied to power distribution networks (PDNs) by combining the validated equivalent‐circuit model and that TSV‐based PDN impedance is compared with the traditional one. By virtue of the large capacitance and low inductance of the 2‐bit CNT TSV, the PDN impedance of the 3‐D IC can be suppressed significantly and the anti‐resonant frequency can be increased.

show abstract

“…The capacitance C OA can be obtained by Cheng et al. [13].