An FPGA implementation of NIST 256 prime field ECC processor

Hasan

et al. 2020

Sensors

With the swift evolution of wireless technologies, the demand for the Internet of Things (IoT) security is rising immensely. Elliptic curve cryptography (ECC) provides an attractive solution to fulfill this demand. In recent years, Edwards curves have gained widespread acceptance in digital signatures and ECC due to their faster group operations and higher resistance against side-channel attacks (SCAs) than that of the Weierstrass form of elliptic curves. In this paper, we propose a high-speed, low-area, simple power analysis (SPA)-resistant field-programmable gate array (FPGA) implementation of ECC processor with unified point addition on a twisted Edwards curve, namely Edwards25519. Efficient hardware architectures for modular multiplication, modular inversion, unified point addition, and elliptic curve point multiplication (ECPM) are proposed. To reduce the computational complexity of ECPM, the ECPM scheme is designed in projective coordinates instead of affine coordinates. The proposed ECC processor performs 256-bit point multiplication over a prime field in 198,715 clock cycles and takes 1.9 ms with a throughput of 134.5 kbps, occupying only 6543 slices on Xilinx Virtex-7 FPGA platform. It supports high-speed public-key generation using fewer hardware resources without compromising the security level, which is a challenging requirement for IoT security.

Section: Performance Comparisonmentioning

confidence: 99%

“…In comparison with this multiplier, our proposed modular multiplier performs single multiplication in 1.45

Section: Performance Comparisonmentioning

confidence: 99%

Design and Implementation of High-Performance ECC Processor with Unified Point Addition on Twisted Edwards Curve

Islam

Hasan

et al. 2020

Sensors

“…It is progressively becoming a more attractive alternative in the past few years to traditional RSA cryptosystems, because ECC can provide the same level of security as the traditional RSA cryptosystem with significantly smaller keys and area. Besides, less memory and hardware resources are required to implement ECC [7–9]. High‐performance finite‐field modular arithmetic (FFMA), e.g.…”

Section: Introductionmentioning

confidence: 99%

“…Over the decades, numerous FPGA‐based implementations of ECPs over a prime field

F_{p}

have been proposed in the literature [4–7, 13, 15–20]. A scalable FPGA‐based implementation of ECPs was presented in [4, 15, 18] that can support all five ECs over a prime field recommended by NIST.…”

Section: Introductionmentioning

confidence: 99%

High‐throughput multi‐key elliptic curve cryptosystem based on residue number system

Asif

IET Computers & Digital Techniques

Kong

2017

Public-key cryptosystems such as elliptic curve cryptography (ECC) and Rivest-Shamir-Adleman (RSA) are widely used for data security in computing systems. ECC provides a high level of security with a much smaller key than RSA, which makes ECC a preferred choice in many applications. This study proposes a multi-key ECC based on the residue number system. The proposed architecture employees deep pipelining to allow the concurrent encryption of 21 keys. The proposed architectures are implemented on two different field programmable gate array (FPGA) platforms and results are compared with existing ECC architectures. The proposed implementation on Virtex-7 FPGA achieves a throughput of 1816 kbps at a clock frequency of 73 MHz.

“…For example, a 256‐bit ECC over a prime field provides the same level of security as a 3072‐bit RSA. In addition, less memory and hardware resources are required to implement elliptic curve cryptosystems [6–9]. This smart and attractive feature makes ECC very popular for resource‐constrained devices such as smart cards, credit cards, pagers, personal digital assistants, and cellular phones.…”

Section: Introductionmentioning

confidence: 99%

High‐performance elliptic curve cryptography processor over NIST prime fields

IET Computers & Digital Techniques

Kong

Saeedi

et al. 2016

This study presents a description of an efficient hardware implementation of an elliptic curve cryptography processor (ECP) for modern security applications. A high‐performance elliptic curve scalar multiplication (ECSM), which is the key operation of an ECP, is developed both in affine and Jacobian coordinates over a prime field of size p using the National Institute of Standards and Technology standard. A novel combined point doubling and point addition architecture is proposed using efficient modular arithmetic to achieve high speed and low hardware utilisation of the ECP in Jacobian coordinates. This new architecture has been synthesised both in application‐specific integrated circuit (ASIC) and field‐programmable gate array (FPGA). A 65 nm CMOS ASIC implementation of the proposed ECP in Jacobian coordinates takes between 0.56 and 0.73 ms for 224‐bit and 256‐bit elliptic curve cryptography, respectively. The ECSM is also implemented in an FPGA and provides a better delay performance than previous designs. The implemented design is area‐efficient and this means that it requires not many resources, without any digital signal processing (DSP) slices, on an FPGA. Moreover, the area–delay product of this design is very low compared with similar designs. To the best of the authors’ knowledge, the ECP proposed in this study over Fp performs better than available hardware in terms of area and timing.