An improved energy efficient SRAM cell for access over a wide frequency range

Nayak, Debasish; Acharya, Debiprasad Priyabrata; Mahapatra, Kamalakanta

doi:10.1016/j.sse.2016.09.016

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Different Circuit Approaches1

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2016

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Cited by 16 publications

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“…Debiprasad Priyabrata Acharya et al [2]. Here, two novel 8T SRAM cells, low leakage current SRAM cell and low leakage current high threshold voltage SRAM cell are proposed to offer high energy efficiency.…”

Section: Different Circuit Approachesmentioning

confidence: 99%

Analysis of 6T SRAM Cell in Different Technologies

Rath¹,

Panda²

2017

CCS Archive

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Static random access memory (SRAM) is an important component of embedded cache memory of handheld digital devices. SRAM has become major data storage device due to its large storage density and less time to access. Exponential growth of low power digital devices has raised the demand of low voltage low power SRAM. This paper presents design and implementation of 6T SRAM cell in 180 nm, 90 nm and 45 nm standard CMOS process technology. The simulation has been done in Cadence Virtuoso environment. The performance analysis of SRAM cell has been evaluated in terms of delay, power and static noise margin (SNM).

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Section: Different Circuit Approachesmentioning

confidence: 99%