An improved reciprocal approximation algorithm for a Newton Raphson divider

Agrawal, Gaurav; Khandelwal, Ankit; Swartzlander, Earl E.

doi:10.1117/12.731650

Cited by 12 publications

(5 citation statements)

References 6 publications

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“…At this time, the bitwidth sum of C 0 and C 1 are minimal. In our case, the sets (17,8) and (16,9) can drop into the error bound with the same LUT area. However, C 1 is also used in the following multiplication operation, so for limiting the area of partial product unit the set (17,8) is chosen in this paper.…”

Section: Error Analysis For Linear-degree Approximationmentioning

confidence: 90%

“…While Ref. 16 uses Taylorseries algorithm to obtain an accurate initial seed value and performs a single NR iteration to get the¯nal result. A fused°oating-point multiply/divide/square root unit based on Taylor-series expansion algorithm was introduced in Ref.…”

Section: Related Workmentioning

confidence: 99%

“…19 Although the radix-8 multiplier is even faster than that of the radix-4 multiplier, it results in large area cost. 16 Therefore, radix-4 multiplier is a better trade-o® between the area cost and performance. As illustrated in the right half of Fig.…”

Section: Architecture Of Double-precision Dividermentioning

confidence: 99%

See 2 more Smart Citations

An Area-Efficient Unified Architecture for Multi-Functional Double-Precision Floating-Point Computation

Guo

Cui

et al. 2015

J CIRCUIT SYST COMP

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In this paper, we propose a uni¯ed architecture for computation of double-precision°oatingpoint division, reciprocal, square root, inverse square root and multiplication with a signi¯cant area reduction. First, a double-precision multiplication-based divider, the common datapath shared with these arithmetic computations, is optimized by a modi¯ed Goldschmidt algorithm to achieve better area e±ciency. In this algorithm, a linear-degree minimax approximation instead of second-degree is used to obtain a 15-bit precision estimate of the reciprocal so that we can get a rather small lookup table (LUT) as well as reduced amount of computation when accumulating the partial products. Two Goldschmidt iterations specially designed for hardware reuse are performed to gain the¯nal accurate result of division. By virtue of the pipelined processing, the time cost for the two iterations is minimized. Second, a recon¯gurable datapath with a little extra area cost is introduced to dynamically support multiple double-precision computations by executing the optimized divider iteratively. The design is¯nally implemented and synthesized in SMIC 0.13-m CMOS process. The experimental results show that the proposed design can achieve a speed of 400 MHz with area of 61.6 K logic gates and 9-Kb LUT. Compared with other works, the area e±ciency (performance/area ratio) of the proposed uni¯ed architecture is increased by about 20% in average, which is a better performance-area trade-o® for embedded microprocessors.

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Section: Error Analysis For Linear-degree Approximationmentioning

confidence: 90%

Section: Related Workmentioning

confidence: 99%

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An Area-Efficient Unified Architecture for Multi-Functional Double-Precision Floating-Point Computation

Guo

Cui

et al. 2015

J CIRCUIT SYST COMP

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“…The number of iterations required to converge to an acceptable answer using the Newton-Raphson reciprocal algorithm described above depends on the accuracy of the approximation [5]. Two algorithms were tested for calculating the initial estimates.…”

Section: Initial Estimatementioning

confidence: 99%

Field Programmable Gate Arrays

Bailey

2011

Design for Embedded Image Processing on FPGAs

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“…It is necessary to calculate the reciprocal (1/A) as part the calculation of K which is the Kalman gain or blending factor [21], see Listing III. 5. Note, A is not a fundamental part of the Kalman Filter; it exists only as a sub-calculation of K. A problem arises when performing division in binary.…”

Section: The Reciprocal Functionmentioning

confidence: 99%

Field-programmable gate arrays

Hauck¹

AccessScience

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On today's modern battlefield, the ability to adapt is critical. The asymmetric threats that we now face require that we have the ability to evolve and field new technology quickly and reliably. The Kalman filter is an important algorithm often used in target tracking applications to estimate the future behavior of a system based on a series of past behaviors. There exists an urgent need to provide a flexible Kalman filter implementation in a portable yet synthesizable design. A one dimensional Kalman Filter algorithm provided in Matlab is used as the basis for the Very High Speed Integrated Circuit Hardware Description Language (VHDL) model. The JAVA programming language is used to create the VHDL code that describes the Kalman filter in hardware which allows for maximum flexibility. The internal parameters of the filter such as process noise covariance, measurement noise covariance, data width, and data shape can be adjusted to achieve an optimal design to fit any requirement. A one-dimensional behavioral model of the Kalman Filter is described, as well as a one-dimensional and synthesizable register transfer level (RTL) model with optimizations for speed, area, and power. These optimizations are achieved by a focus on parallelization as well as careful Kalman filter sub-module algorithm selection. Newton-Raphson reciprocal is the chosen algorithm for a fundamental aspect of the Kalman filter, which allows efficient high-speed computation of reciprocals within the overall system. The Newton-Raphson method is also expanded for use in calculating square-roots in an optimized and synthesizable two-dimensional VHDL implementation of the Kalman filter. The two-dimensional Kalman filter expands on the one-dimensional implementation allowing for the tracking of targets on a real-world Cartesian coordinate system. An additional goal of this research is to perform an investigation and characterization of how to realize optimal real-time target tracking algorithms in hardware, This thesis would not have been possible if not for the help and patience of my family, friends, and professors. First and foremost, I need to thank my wife for her encouragement and understanding. I also need to thank my three children, who never forgot who I was despite many prolonged absences and whose hugs and smiles could bring me up in an instant. I made many new friends here at AFIT that supported me and helped all along the way; thanks guys. I had many great professors to whom I extend a sincere thank you. In particular, I would like to thank Dr. Yong Kim for his mentorship and guidance down this long difficult road.

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An improved reciprocal approximation algorithm for a Newton Raphson divider

Cited by 12 publications

References 6 publications

An Area-Efficient Unified Architecture for Multi-Functional Double-Precision Floating-Point Computation

An Area-Efficient Unified Architecture for Multi-Functional Double-Precision Floating-Point Computation

Field Programmable Gate Arrays

Field-programmable gate arrays

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