An innovative low-power high-performance programmable signal processor for digital communications

Moreno, Jaime H.; Zyuban, Victor; Shvadron, U.; Neeser, F. D.; Derby, J.; Ware, Malcolm; Kailas, Krishnan; Zaks, Ayal; Geva, Amir B.; Ben-David, S.; Asaad, Sameh; Fox, Thomas W.; Littrell, Daniel; Biberstein, Marina; Naishlos, Dorit; Hunter, Hillery C.

doi:10.1147/rd.472.0299

Cited by 28 publications

(21 citation statements)

References 24 publications

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“…The solution in [14] has a larger register file than ePUMA. This is similar to the solution in the eLite DSP architecture [16], that uses vector pointers into the vector register file. They all use a load/store model.…”

Section: Related Workmentioning

confidence: 93%

Automatic Permutation for Arbitrary Static Access Patterns

Sohl

Wang

Karlsson

et al. 2012

2012 IEEE 10th International Symposium on Parallel and Distributed Processing With Applications

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A significant portion of the execution time on current SIMD and VLIW processors is spent on data access rather than instructions that perform actual computations. The ePUMA 1 architecture provides features that allow arbitrary data elements to be accessed in parallel as long as the elements reside in different memory banks. Using permutation to move data elements that are accessed in parallel, the overhead from memory access can be greatly reduced; and, in many cases completely removed. This paper presents a practical method for automatic permutation based on Integer Linear Programming (ILP). No assumptions are made about the structure of the access patterns other than their static nature. Methods for speeding up the solution time for periodic access patterns and reusing existing solutions are also presented. Benchmarks for e.g. FFTs show speedups of up to 3.4 when using permutation compared to regular implementations.

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Section: Related Workmentioning

confidence: 93%

Automatic Permutation for Arbitrary Static Access Patterns

Sohl

Wang

Karlsson

et al. 2012

2012 IEEE 10th International Symposium on Parallel and Distributed Processing With Applications

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“…However, the register file is quite large. The approach in [58] is quite similar to the approach for the eLite DSP architecture presented in [60], where the register file can be addressed by vector pointers.…”

Section: Related Workmentioning

confidence: 99%

Efficient Compilation for Application Specific Instruction set DSP Processors with Multi-bank Memories

Sohl

2015

Linköping Studies in Science and Technology. Dissertations

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Modern signal processing systems require more and more processing capacity as times goes on. Previously, large increases in speed and power efficiency have come from process technology improvements. However, lately the gain from process improvements have been greatly reduced.Currently, the way forward for high-performance systems is to use specialized hardware and/or parallel designs.Application Specific Integrated Circuits (ASICs) have long been used to accelerate the processing of tasks that are too computationally heavy for more general processors. The problem with ASICs is that they are costly to develop and verify, and the product life time can be limited with newer standards. Since they are very specific the applicable domain is very narrow.More general processors are more flexible and can easily adapt to perform the functions of ASIC based designs. However, the generality comes with a performance cost that renders general designs unusable for some tasks. The question then becomes, how general can a processor be while still being power efficient and fast enough for some particular domain?Application Specific Instruction set Processors (ASIPs) are processors that target a specific application domain, and can offer enough performance with power efficiency and silicon cost that is comparable to ASICs.The flexibility allows for the same hardware design to be used over several system designs, and also for multiple functions in the same system, if some functions are not used simultaneously.iii iv One problem with ASIPs is that they are more difficult to program than a general purpose processor, given that we want efficient software.Utilizing all of the features that give an ASIP its performance advantage can be difficult at times, and new tools and methods for programming them are needed.This thesis will present ePUMA (embedded Parallel DSP platform with Unique Memory Access), an ASIP architecture that targets algorithms with predictable data access. These kinds of algorithms are very common in e.g. baseband processing or multimedia applications. The primary focus will be on the specific features of ePUMA that are utilized to achieve high performance, and how it is possible to automatically utilize them using tools. The most significant features include data permutation for conflict-free data access, and utilization of address generation features for overhead free code execution. This sometimes requires specific information; for example the exact sequences of addresses in memory that are accessed, or that some operations may be performed in parallel. This is not always available when writing code using the traditional way with traditional languages, e.g. C, as extracting this information is still a very active research topic. In the near future at least, the way that software is written needs to change to exploit all hardware features, but in many cases in a positive way. Often the problem with current methods is that code is overly specific, and that a more general abstractions are actually easier to ge...

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“…The register organization described in this work differs from other hierarchical [16] and distributed [13] organizations by distributing the register files at every level of the hierarchy and by using small (4-entry) register files, each associated with and located within a single functional unit, at the lowest level. Like index registers, the vector pointer registers described in [11] can be automatically updated when used to access a register file. The register organization described in this work differs because it allows the XRF registers to be directly accessed, bypassing the index registers, when data are accessed irregularly; this allows the XRF registers to hold working sets that contain both scalar and vector operands.…”

Section: Related Workmentioning

confidence: 99%

An Energy-Efficient Processor Architecture for Embedded Systems

Balfour

Dally

Black-Schaffer

et al. 2008

IEEE Comput. Arch. Lett.

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Abstract-We present an efficient programmable architecture for compute-intensive embedded applications. The processor architecture uses instruction registers to reduce the cost of delivering instructions, and a hierarchical and distributed data register organization to deliver data. Instruction registers capture instruction reuse and locality in inexpensive storage structures that are located near to the functional units. The data register organization captures reuse and locality in different levels of the hierarchy to reduce the cost of delivering data. Exposed communication resources eliminate pipeline registers and control logic, and allow the compiler to schedule efficient instruction and data movement. The architecture keeps a significant fraction of instruction and data bandwidth local to the functional units, which reduces the cost of supplying instructions and data to large numbers of functional units. This architecture achieves an energy efficiency that is 23× greater than an embedded RISC processor.Index Terms-energy-efficient embedded processor architecture, instruction registers, hierarchical and distributed register organization

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An innovative low-power high-performance programmable signal processor for digital communications

Cited by 28 publications

References 24 publications

Automatic Permutation for Arbitrary Static Access Patterns

Automatic Permutation for Arbitrary Static Access Patterns

Efficient Compilation for Application Specific Instruction set DSP Processors with Multi-bank Memories

An Energy-Efficient Processor Architecture for Embedded Systems

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