2020
DOI: 10.1016/j.vlsi.2020.03.004
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An innovative two-stage data compression scheme using adaptive block merging technique

Abstract: Test data has increased enormously owing to the rising on-chip complexity of integrated circuits. It further increases the test data transportation time and tester memory. The non-correlated test bits increase the issue of the test power. This paper presents a two-stage block merging based test data minimization scheme which reduces the test bits, test time and test power. A test data is partitioned into blocks of fixed sizes which are compressed using two-stage encoding technique. In stage one, successive blo… Show more

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Cited by 3 publications
(3 citation statements)
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“…A huge TAV is stored in the tester's memory as well as then transfer among tester's unit as well as circuit under test (CUT) during SoC testing. Test data compression schemes [21] act as a hopeful solution for solving the issue of TDV reduction to SoCs. Furthermore, it lessens the TAT, peak as well as average power.…”
Section: Introductionmentioning
confidence: 99%
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“…A huge TAV is stored in the tester's memory as well as then transfer among tester's unit as well as circuit under test (CUT) during SoC testing. Test data compression schemes [21] act as a hopeful solution for solving the issue of TDV reduction to SoCs. Furthermore, it lessens the TAT, peak as well as average power.…”
Section: Introductionmentioning
confidence: 99%
“…So, several test compaction methods [14] possess the capability to control the test data volume in a great extent. Then, the compressed experimental sets might attain less detection of non-modeled physical faults [9,21]. The BIST is widely used for memory testing and is not logical BIST requires more test time [7].…”
Section: Introductionmentioning
confidence: 99%
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