An innovative ultra low voltage sub-32nm SRAM voltage sense amplifier in DG-SOI technology

Pranav, P.; Giraud, B.; Amara, Ayed Ben

doi:10.1109/mwscas.2008.4616772

Cited by 3 publications

(3 citation statements)

References 7 publications

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“…Sense delay is one of the important parameter that decides performance of a sense amplifier. Sense delay is defined [22] as time at which sense enable signal rises to V dd /2 to the time at which output drops to V dd /2.…”

Section: Impact Of Process Variationsmentioning

confidence: 99%

Low Power Double Gate Fin FET Based Sense Amplifier

Priyadarshni¹,

Singh²

2015

International Journal of Advanced Research in Computer and Comm

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Abstract:In this paper, a low power independent-gate, process variation tolerant double gate (DG) Fin FET based sense amplifier design has been proposed. As like RHIGSA, new design exploits the DICE (dual interlock cell) latch and the back gate of a double-gate Fin FET (DG Fin FET) device for dynamic compensation against process variation. But, there is change in tail transistor gate connections.,Which is dynamically controlled by intermediate signal in circuit. This design improves the power dissipation and show excellent tolerance to process parameter variations like temperature, V dd , thickness of oxide compared to Radiation hardend IGSA (RHIGSA) circuit and independent gate sense amplifier (IGSA). Proposed technique consumes 29.108% less power compare to RHIGSA.

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Section: Impact Of Process Variationsmentioning

confidence: 99%

Low Power Double Gate Fin FET Based Sense Amplifier

Priyadarshni¹,

Singh²

2015

International Journal of Advanced Research in Computer and Comm

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“…Sense delay is defined [19] as time at which sense enable signal rises to V dd /2 to the time at which output drops to V dd /2 as shown in Fig. 9.…”

Section: Sensing Delaymentioning

confidence: 99%

A low-noise, process-variation-tolerant double-gate FinFET based sense amplifier

Rathod

Saxena

Dasgupta

2011

Microelectronics Reliability

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“…Ultra-low voltage processors [2], [3], [4], [5] and memories [6] [7] were reported, illustrating the costs of the supply voltage lowering: speed divided by 1000x and variability increased by 6x. The major drawback still remains the complexity of those designs, using dedicated logic, technology or flow.…”

Section: Introductionmentioning

confidence: 99%

A 240mV 1MHz, 340mV 10MHz, 40nm CMOS, 252 bits frame decoder using ultra-low voltage circuit design platform

Clerc

Abouzeid

Argoud

et al. 2011

2011 18th IEEE International Conference on Electronics, Circuits, and Systems

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A low cost Ultra Low Voltage design implemented using standard CAD tools with adapted margins is presented. Critical path replica rings have been measured to ensure models validity at ultra-low voltages, on the 0 • C to 50 • C temperature range. The observed behavior and mismatch compared to CAD simulations enabled us to define the margins to be used for the standard circuit implementation flow. We then derived a cell library focusing our effort on latches and level shifters. A 10k gates, 1k flip-flops demonstrator was designed and measured. Its functional voltage range is extended by 4x down to 0.24V, reducing the dynamic power by a factor 14x versus nominal. Forward Body Biasing and Temperature effect on minimum voltage for both worst die and die population average are reported.

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An innovative ultra low voltage sub-32nm SRAM voltage sense amplifier in DG-SOI technology

Cited by 3 publications

References 7 publications

Low Power Double Gate Fin FET Based Sense Amplifier

Low Power Double Gate Fin FET Based Sense Amplifier

A low-noise, process-variation-tolerant double-gate FinFET based sense amplifier

A 240mV 1MHz, 340mV 10MHz, 40nm CMOS, 252 bits frame decoder using ultra-low voltage circuit design platform

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