A 240mV 1MHz, 340mV 10MHz, 40nm CMOS, 252 bits frame decoder using ultra-low voltage circuit design platform

Abstract

A low cost Ultra Low Voltage design implemented using standard CAD tools with adapted margins is presented. Critical path replica rings have been measured to ensure models validity at ultra-low voltages, on the 0 • C to 50 • C temperature range. The observed behavior and mismatch compared to CAD simulations enabled us to define the margins to be used for the standard circuit implementation flow. We then derived a cell library focusing our effort on latches and level shifters. A 10k gates, 1k flip-flops demonstrator was designed and measured. Its functional voltage range is extended by 4x down to 0.24V, reducing the dynamic power by a factor 14x versus nominal. Forward Body Biasing and Temperature effect on minimum voltage for both worst die and die population average are reported.