An Integrated 0.6–4.6 GHz, 5–7 GHz, 10–14 GHz, and 20–28 GHz Frequency Synthesizer for Software-Defined Radio Applications

Osmany, Sabbir A.; Peters, Frank; Scheytt, J. Christoph

doi:10.1109/jssc.2010.2051476

Cited by 53 publications

(26 citation statements)

References 31 publications

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“…Multi-modulus local oscillator generation (LOGEN) plays an important role in wideband frequency synthesizers [1,2]. In the LOGEN, wideband divide-by-1.5 is a challenging block to realize the quadrature-output divide-by-3 divider [1,2].…”

Section: Introductionmentioning

confidence: 99%

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0.3–4.4 GHz wideband CMOS frequency divide-by-1.5 with optimized CML-XOR gate

Chen

Guo

Lai

et al. 2017

IEICE Electron. Express

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An ultra-wideband differential divide-by-1.5 divider based on current-mode logic (CML) is proposed. It consists of a divide-by-3 circuit and an optimized CML-XOR gate. Fully symmetric and differential structure is proposed to extend upper bound working frequency. In the CML-XOR gate, two identical Gilbert cells with optimized eight-input signals are developed to strengthen the pull-down force, which benefits the high-speed division. Fabricated in TSMC 180 nm CMOS process, this divider achieves an operating frequency of 0.3-4.4 GHz for 0 dBm input, and consumes 4.14 mW from 1.8 V supply. The chip size is 0.02 mm 2 .

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Section: Introductionmentioning

confidence: 99%

“…In the LOGEN, wideband divide-by-1.5 is a challenging block to realize the quadrature-output divide-by-3 divider [1,2]. Semi-dynamic structure is mostly used to realize the divide-by-1.5 [1,3].…”

Section: Introductionmentioning

confidence: 99%

0.3–4.4 GHz wideband CMOS frequency divide-by-1.5 with optimized CML-XOR gate

Chen

Guo

Lai

et al. 2017

IEICE Electron. Express

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“…The first proposed idea of an SDR, developed by Mitola [3], is to perform all RF and baseband signal processing designs in both analog and digital domains. It brings the flexibility, cost efficiency and enhanced power in order to carry forward communication, resulting in benefits to the service providers [4]. The extensive progress of CMOS technology has enabled its application in SDR wireless networks.…”

Section: Introductionmentioning

confidence: 99%

Co-design Approach for Wide-Band Asymmetric Cross Shaped Slotted Patch Antenna with LNA

Kumar

Kanaujia²,

Dwari

et al. 2015

Wireless Pers Commun

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The proposed work presents a co-design approach for a new asymmetric rectangular cross shaped slotted patch antenna with low noise amplifier that occupies 17.2-25.8 GHz wide-band for SDR applications. This co-design approach minimizes the chip area and noise and also improves integration system over the bandwidth of 8.6 GHz. Three different architectures have been designed in this work. Firstly, a two stage CMOS CG-CS LNA is designed using a technique of series-parallel resonant network as an input matching network and as inter-stage matching network between CG and CS LNA. In second architecture stage, a rectangular shaped microstrip antenna is designed and a slot of asymmetric cross shape is cut on the patch antenna. In third architecture the slotted antenna is integrated with low noise amplifier in order to form a co-design approach in which series-parallel resonant network is used as a band pass filter between slotted patch antenna and LNA. A two-stage CMOS LNA design is simulated and layout is made using foundry design kit for the TSMC 65 nm CMOS process in ADS.v.12. A simulation result of LNA achieves S 11 of -21.4 dB with gain ranging from 7.4 to 21.3 dB over the wide-band of 19.

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“…They limit the voltage amplitudes of oscillators and the voltage swing of the charge pump transistors. In multi-band multi-standard base stations, for example, phase noise and spur performance is of paramount importance, whereas power consumption is less critical [9]. A low phase noise at small and large frequency offsets is also crucial in satellite applications.…”

Section: Introductionmentioning

confidence: 99%

An integrated 10 GHz low-noise phase-locked loop with improved PVT tolerance

Osmany

Scheytt

et al. 2011

Analog Integr Circ Sig Process

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An integrated phase-locked loop (PLL) with low phase noise is presented, which is robust with respect to variations of device parameters with process, supply voltage, and temperature (PVT). The low-noise CMOS voltage-controlled oscillator (VCO) employs two varactors for fine and coarse tuning. By using a CMOS charge pump with output biasing, the dc fine tuning voltage of the VCO and the loop dynamics of the PLL are well defined and fairly independent of PVT variations. Device noise in the charge pump and linearity of the phase detector are much improved by a two-transistor charge pump architecture for fine tuning. We measured a phase noise below -131 dBc/ Hz at 10 MHz offset and below -94 dBc/Hz at 10 kHz offset over a tuning range of 1.2 GHz. An integrated phase error below 0.6°was measured, corresponding to an rms jitter below 160 fs. The chip was produced in a 0.25 lm low-cost SiGe BiCMOS technology, occupies a chip area of 2.25 mm 2 and draws 60 mA from a 3 V supply.

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An Integrated 0.6–4.6 GHz, 5–7 GHz, 10–14 GHz, and 20–28 GHz Frequency Synthesizer for Software-Defined Radio Applications

Cited by 53 publications

References 31 publications

0.3–4.4 GHz wideband CMOS frequency divide-by-1.5 with optimized CML-XOR gate

0.3–4.4 GHz wideband CMOS frequency divide-by-1.5 with optimized CML-XOR gate

Co-design Approach for Wide-Band Asymmetric Cross Shaped Slotted Patch Antenna with LNA

An integrated 10 GHz low-noise phase-locked loop with improved PVT tolerance

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