An integrated 10 GHz low-noise phase-locked loop with improved PVT tolerance

Abstract

An integrated phase-locked loop (PLL) with low phase noise is presented, which is robust with respect to variations of device parameters with process, supply voltage, and temperature (PVT). The low-noise CMOS voltage-controlled oscillator (VCO) employs two varactors for fine and coarse tuning. By using a CMOS charge pump with output biasing, the dc fine tuning voltage of the VCO and the loop dynamics of the PLL are well defined and fairly independent of PVT variations. Device noise in the charge pump and linearity of the phase detector are much improved by a two-transistor charge pump architecture for fine tuning. We measured a phase noise below -131 dBc/ Hz at 10 MHz offset and below -94 dBc/Hz at 10 kHz offset over a tuning range of 1.2 GHz. An integrated phase error below 0.6°was measured, corresponding to an rms jitter below 160 fs. The chip was produced in a 0.25 lm low-cost SiGe BiCMOS technology, occupies a chip area of 2.25 mm 2 and draws 60 mA from a 3 V supply.

Design and layout strategies for integrated frequency synthesizers with high spectral purity

“…As evident from (2), a high CP current minimizes the phase noise contribution of the devices in the CP. This has been verified in a 10 GHz CMOS PLL [18]. Figure 2 shows the phase noise spectrum of the 10.5 GHz PLL for different CP currents.…”

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Fig. 2. Measured PLL phase noise at 10.5 GHz for different CP currents [18]. DC offset current at the CP output is disabled.

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“…When realized as a CMOS inverter chain, the first inverter should have a large g m as evident from (3). Based on extensive investigations in the context of [18], [10], and [4], we recommend an aspect ratio W / L on the order of 100 for the MOSFETs in the input inverter. The following inverters may use smaller transistors, since they are less sensitive to additive noise due to the large signal slopes at their inputs.…”

Self-calibrating highly sensitive dynamic capacitance sensor: towards rapid sensing and counting of particles in laminar flow systems

“…A large coarsetuning capacitor C coarse is responsible for the compensating Process-Voltage-Temperature (PVT) variations. 22 A small finetuning capacitor C fine is used to detect small frequency changes. Moreover, an additional small varactor C mod is used to emulate the dynamic capacitance change for the initial measurements independent of an integrated microfluidic channel.…”

“…For a detailed understanding of the circuit the readers are referred to research works based on circuit theory and applications. 22,23 However, a brief overview of the architecture is given with more emphasis on the modelling and analytical derivation of the differential equations governing the frequency demodulation architecture.…”