An Integrated Framework for Application Independent Testing of FPGA Interconnect

Banik, Shukla; Roy, Suchismita; Sen, Bibhash

doi:10.1007/s10836-019-05827-7

Cited by 3 publications

(2 citation statements)

References 15 publications

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“…Table 1 pr s used in this paper along with their respective explanations. FPGAs are composed primarily of modules, such as configurable logic blocks (CLBs), input-output blocks (IOBs), interconnect resources (IRs), and block random access memory (BRAM) [9,10]. The CLB is the core resource of the entire FPGA, consisting mainly of programmable resources, such as look-up tables (LUTs), multiplexers, carry chains, and flip-flops, to implement different logical functions.…”

Section: Introductionmentioning

confidence: 99%

Research on an Intelligent Test Method for Interconnect Resources in an FPGA

Xie

Qi²,

Lin

et al. 2023

Applied Sciences

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With the rapid development of integrated circuit production technology, the scale of FPGA circuits has expanded to billions of gates. The complexity of the internal resource structures in the FPGAs (field programmable gate arrays) is continually increasing, and there is an increasing possibility of various faults in these circuits, especially in interconnect resources. These occupy more than 80% of a chip’s area and have the highest fault rate. To ensure the reliability of the FPGAs, it is very important to perform high-coverage testing on the interconnect resources within them. This article uses AMD Xilinx’s Kintex-7 series FPGA as the research object and proposes a deep-priority algorithm based on graph-based models and improved priority algorithms to intelligently wire the FPGA interconnected resources. The routing results were produced using a configuration script written in the XDL language, and the FPGA configuration and testing were conducted accordingly. This approach achieved a high coverage and intelligent testing for the interconnect resources in the FPGAs.

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Section: Introductionmentioning

confidence: 99%

Research on an Intelligent Test Method for Interconnect Resources in an FPGA

Xie

Qi²,

Lin

et al. 2023

Applied Sciences

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show abstract

“…With the characteristic of rapid hardware diagnosis, build-in self-test (BIST) was gradually used to test single lines [7]. It implemented the TPG and the ORA by configurable logic block (CLB) resources, thus greatly reducing the consumption of I/O resources [8][9][10][11][12]. Sun et al [8] proposed a parity-based BIST approach for Xilinx 4000 series FPGAs.…”

Section: Introductionmentioning

confidence: 99%

Research on Hex Programmable Interconnect Points Test in Island-Style FPGA

et al. 2020

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With the decreasing size of manufacturing process, the scale of island-style field programmable gate array (FPGA) becomes larger, which leads to the increasing complexity of FPGA routing resources, especially hex programmable interconnect points (PIPs). Hex PIPs which span six tiles of the island-style FPGA have complex interconnect rules. Accordingly, research on complete hex PIPs test is rarely involved in the study of routing resources test. Therefore, this paper analyzes the hex PIPs architecture of the island-style FPGA, summarizes the interconnect rules of the hex PIPs mathematically in a two-dimensional coordinate system, and presents two proper test algorithms at the same time. The hex PIPs are divided into three directions, that is, horizontal, vertical, and oblique. According to the proposed coordinate equations, a cycle test structure in the horizontal and vertical directions and a test structure with partial-cascade patterns in the oblique direction are designed respectively. It is concluded that the proposed methods can achieve 100% fault coverage for the hex PIPs test in all directions, and the configuration number for hex lines test with the same methods is significantly decreased than previous researches.

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PUF: a new era in IoT security

Sen

2020

CSIT

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An Integrated Framework for Application Independent Testing of FPGA Interconnect

Cited by 3 publications

References 15 publications

Research on an Intelligent Test Method for Interconnect Resources in an FPGA

Research on an Intelligent Test Method for Interconnect Resources in an FPGA

Research on Hex Programmable Interconnect Points Test in Island-Style FPGA

PUF: a new era in IoT security

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