An investigation of capacitance-voltage hysteresis in metal/high-k/In0.53Ga0.47As metal-oxide-semiconductor capacitors

Abstract

In this work, we present the results of an investigation into charge trapping in metal/high-k/In0.53Ga0.47As metal-oxide-semiconductor capacitors (MOS capacitors), which is analysed using the hysteresis exhibited in the capacitance-voltage (C-V) response. The availability of both n and p doped In0.53Ga0.47As epitaxial layers allows the investigation of both hole and electron trapping in the bulk of HfO2 and Al2O3 films formed using atomic layer deposition (ALD). The HfO2/In0.53Ga0.47As and Al2O3/In0.53Ga0.47As MOS capacitors exhibit an almost reversible trapping behaviour, where the density of trapped charge is of a similar level to high-k/In0.53Ga0.47As interface state density, for both electrons and holes in the HfO2 and Al2O3 films. The experimental results demonstrate that the magnitude of the C-V hysteresis increases significantly for samples which have a native oxide layer present between the In0.53Ga0.47As surface and the high-k oxide, suggesting that the charge trapping responsible for the C-V hysteresis is taking place primarily in the interfacial oxide transition layer between the In0.53Ga0.47As and the ALD deposited oxide. Analysis of samples with a range of oxide thickness values also demonstrates that the magnitude of the C-V hysteresis window increases linearly with the increasing oxide thickness, and the corresponding trapped charge density is not a function of the oxide thickness, providing further evidence that the charge trapping is predominantly localised as a line charge and taking place primarily in the interfacial oxide transition layer located between the In0.53Ga0.47As and the high-k oxide. (C) 2013 AIP Publishing LLC

Multi-frequency inversion-charge pumping for charge separation and mobility analysis in high-k/InGaAs metal-oxide-semiconductor field-effect transistors

“…Recent studies have indicated the presence of border traps in high-k/InGaAs MOS structures using C-V, [15][16][17][18][19] charge pumping 20 and high-frequency transconductance 21 measurements. Evidence of the presence of border traps can also be observed in an I d -V g characteristic, where it is manifest as a hysteresis loop.…”

Post Plasma Oxidation Processed ALD Al2O3/Hf1-xZrxO2Thin Films on Ge Substrates: Reliability

“…It is known that charge-trapping sites located in the dielectrics and substrate interface are responsible for C-V hysteresis. 28 Understanding of the hysteresis behavior is particularly important as they represent a physical process that results in device instability and for devices with Ge channel, the level of charge trapping can be comparable or greater than the effect of interface states. 3,28 From Fig.…”

A combined capacitance-voltage and hard x-ray photoelectron spectroscopy characterisation of metal/Al2O3/In0.53Ga0.47As capacitor structures

“…To realise this potential for an improved performance/power consumption ratio it is necessary to study the high-k/III-V gate stack from the perspective of electrically active defect states, which include interface states, fixed charges within the highk oxide and border traps near/at the high-k/III-V interface transition layer. [1][2][3] These defects affect MOSFET performance in a range of detrimental ways, 4,5 and possible methods to remove these defects from high-k/III-V MOS system have been extensively studied. [6][7][8][9] Interface properties are of particular interest due to the relatively high density of electrically active interface defects present at this interface, which restricts efficient III-V surface Fermi level movement.…”