“…To continue scaling down p + poly‐Si gates of MOS integrated circuits, it is necessary to create very shallow junctions with strong‐concentrations of electrically active B. Two related processes limit the realization of this goal: (i) the enhanced redistribution of the B during the thermal dopant‐activation annealing, which causes B penetration through thin oxides from the p + poly‐Si gate into the underlying layers 3, and (ii) the formation of electrically inactive B clusters and B precipitates 4,5, which decreases the dopant activation rate. The use of low‐energy doping methods, co‐doping techniques, low thermal annealing temperatures, short annealing times, amorphous‐silicon layers, and thin Nitrogen‐Doped‐Silicon (NiDoS) layers have been practiced to avoid the doping depletion of p + polysilicon gate at the oxide interface 6–8.…”