An Mpi-Based Framework for Parallel Processing of Integrated Circuits Layout Images

Abstract

We consider basic algorithms and processing technologies for integrated circuit layout images. The images represented as a set of frames can regard as a dataflow and the processing are perfectly suited for parallel implementation. We propose a framework architecture for designing parallel systems of image dataflow processing. The framework uses the algorithm of a virtual associative network for increasing processing speed and system throughput during runtime.

Optical imaging and image analysis for high aspect ratio NEMS

“…Knowing likely feature appearance, a suitable image processing strategy may be developed. Feature extraction has been developed for biological [24,25] and medical [26] image analysis, character [27] and fingerprint [28] recognition, PCB inspection [29] and fault detection in integrated circuits [30]. Often the image is filtered to reduce noise [31].…”