An MTJ‐based non‐volatile flip‐flop for high‐performance SoC

Jung, Youngdon; Kim, Jisu; Ryu, Koungmin; Kang, Sungwon; Jung, Seong‐Ook

doi:10.1002/cta.1859

Cited by 21 publications

(15 citation statements)

References 19 publications

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“…MRAM-CMOS NVFFs typically need extra circuits for writing and reading MTJs. Multiple realizations of the extra circuits, which use additional write drivers and sense amplifiers, have been proposed [14,15,16,17]. In [15], two NAND gates, seven inverters, and three NMOS switch transistors are used for the external write driver and the sense amplifier with a significant reduction of D-Q delay.…”

Section: Mram-cmos Non-volatile Flip-flopsmentioning

confidence: 99%

“…Multiple realizations of the extra circuits, which use additional write drivers and sense amplifiers, have been proposed [14,15,16,17]. In [15], two NAND gates, seven inverters, and three NMOS switch transistors are used for the external write driver and the sense amplifier with a significant reduction of D-Q delay. In [16], four NOR gates, four inverters, and 16 NMOS transistors are used to reduce C-Q delay and sensing currents.…”

Section: Mram-cmos Non-volatile Flip-flopsmentioning

confidence: 99%

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Fine-Grained Power Gating Using an MRAM-CMOS Non-Volatile Flip-Flop

Park

Yim

2019

Micromachines

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An area-efficient non-volatile flip flop (NVFF) is proposed. Two minimum-sized Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) and two magnetic tunnel junction (MTJ) devices are added on top of a conventional D flip-flop for temporary storage during the power-down. An area overhead of the temporary storage is minimized by reusing a part of the D flip-flop and an energy overhead is reduced by a current-reuse technique. In addition, two optimization strategies of the use of the proposed NVFF are proposed: (1) A module-based placement in a design phase for minimizing the area overhead; and (2) a dynamic write pulse modulation at runtime for reducing the energy overhead. We evaluated the proposed NVFF circuit using a compact MTJ model targeting an implementation in a 10 nm technology node. Results indicate that area overhead is 6.9 % normalized to the conventional flip flop. Compared to the best previously known NVFFs, the proposed circuit succeeded in reducing the area by 4.1 × and the energy by 1.5 × . The proposed placement strategy of the NVFF shows an improvement of nearly a factor of 2–18 in terms of area and energy, and the pulse duration modulation provides a further energy reduction depending on fault tolerance of programs.

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Section: Mram-cmos Non-volatile Flip-flopsmentioning

confidence: 99%

Section: Mram-cmos Non-volatile Flip-flopsmentioning

confidence: 99%

Fine-Grained Power Gating Using an MRAM-CMOS Non-Volatile Flip-Flop

Park

Yim

2019

Micromachines

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“…NVFF structures can be divided into two types according to the position of the sensing circuit. One is a merged latch and sensing circuit (MLS) structure [3]- [5], [22], and the other is a separated latch and sensing circuit (SLS) structure [6], [8]- [9], [14]- [15], as shown in Fig. 1.…”

Section: Introductionmentioning

confidence: 99%

“…Among these techniques, this paper focuses on the offset cancellation technique for process variation tolerance. In recent years, several SLS structure-based NVFFs have been reported [6], [8]- [9], [14]- [15]. However, they do not satisfy the target restore yield of 4σ (96.88% yield when 1000 FFs are assumed) and the target read disturbance margin of 6σ (99% yield when 10 000 access per a single cell is assumed by considering the stochastic nature of MTJs) at all corners in the NTV region simultaneously.…”

Section: Introductionmentioning

confidence: 99%

Novel MTJ-Based Sensing Inverter Variation Tolerant Nonvolatile Flip-Flop in the Near-Threshold Voltage Region

Choi

2020

IEEE Access

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In recent years, the low power design of Internet of Things devices has become increasingly important. The most basic method to implement a low power design is to reduce static power consumption. In this regard, a spin-transfer-torque magnetic-tunnel-junction-based nonvolatile flip-flop (NVFF) is a promising candidate for storing the computing data while the power is off. However, as the technology node scales down, the process variation increases, leading to a restoration failure in previous NVFFs, especially in the near-threshold voltage (NTV) region. For better energy efficiency when operating the NVFF in the NTV region, this paper presents a novel NVFF that guarantees a target restore yield of 4σ and a target read disturbance margin of 6σ in the NTV region (0.6 V supply voltage), along with auto-zeroing and dynamic reference voltage (DRV) techniques, using only a single capacitor to improve the NVFF's restore yield. The Monte Carlo HSPICE simulation results using industry-compatible 28-nm model parameters show that the proposed NVFF satisfies both the target restore yield and the read disturbance margin, saving 44% restoration time compared with the current state-of-the-art NVFF, which does not satisfy the target restore yield despite having offset cancellation characteristic. INDEX TERMS Auto-zeroing, double sensing margin, dynamic reference voltage (DRV), magnetic tunnel junction (MTJ), near-threshold voltage (NTV), nonvolatile flip-flop (NVFF), sensing inverter variation tolerant (SIVT), sensing margin (SM).

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“…Previous work on non-volatile flip-flops was based on the "memristor" [6], [4], on bipolar OxRAM [7], and Magnetic Tunneling Junction (MTJ) devices [8], [9], [10]. All this work considered circuit operation at a high supply voltage, normally corresponding to the CMOS technology's nominal voltage.…”

Section: Introductionmentioning

confidence: 99%

A ReRAM-based non-volatile flip-flop with sub-V<inf>T</inf> read and CMOS voltage-compatible write

Kazi

Meinerzhagen

Gaillardon

et al. 2013

2013 IEEE 11th International New Circuits and Systems Conference (NEWCAS)

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Abstract-The total power budget of Ultra-Low Power (ULP) VLSI Systems-on-Chip (SoCs) is often dominated by the leakage power of embedded memories and pipeline registers, which typically cannot be power-gated during sleep periods as they need to retain data and program state, respectively. On the one hand, supply voltage scaling down to the near-threshold (near-VT) or even to the sub-threshold (sub-VT) domain is a commonly used, efficient technique to reduce both leakage power and active energy dissipation. On the other hand, emerging CMOS-compatible device technologies such as Resistive Memories (ReRAMs) enable non-volatile, on-chip data storage and zero-leakage sleep periods. For the first time, we present a ReRAM-based non-volatile flipflop which is optimized for sub-VT operation. Writing to the ReRAM devices works with a CMOS-compatible supply voltage. Thanks to near-VT and sub-VT operation and as compared to the write energy, which depends on the ReRAM technology, the read consumes only 5.4% of the total read+write energy. Monte Carlo simulations accounting for parametric variations in both the MOS transistors and the ReRAM devices confirm reliable data restore operation from the ReRAM devices at a sub-VT voltage as low as 400 mV, and a standard deviation of up to 5% of the nominal value of the ReRAM resistance.

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An MTJ‐based non‐volatile flip‐flop for high‐performance SoC

Cited by 21 publications

References 19 publications

Fine-Grained Power Gating Using an MRAM-CMOS Non-Volatile Flip-Flop

Fine-Grained Power Gating Using an MRAM-CMOS Non-Volatile Flip-Flop

Novel MTJ-Based Sensing Inverter Variation Tolerant Nonvolatile Flip-Flop in the Near-Threshold Voltage Region

A ReRAM-based non-volatile flip-flop with sub-V<inf>T</inf> read and CMOS voltage-compatible write

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