An n-channel Si-gate integrated circuit technology

Clemens, J.T.; Mowery, G. L.; Doklan, R.H.; Nolen, J.J.; Drobek, J.

doi:10.1109/iedm.1975.188884

Cited by 7 publications

(4 citation statements)

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“…Some detailed profiles obtained from "hi-lo" VPE n-GaAs (modified Read IMPATT material) are also presented. Emphasis is placed on the very high levels of reproducibility required from the profiling technique in this area of application (4,5).…”

Section: Applications Of Electrochemical Methods Formentioning

confidence: 99%

“…It has been observed that this processing scheme produces a bird's beak configuration (1)(2)(3)(4) at the edge of the isolation oxide, and that subsequent gate oxidation (after removal of masking Si3N4) often results in a thinning of the gate oxide next to the isolation oxide. The thinning of the gate oxide has been attributed to the presence of a thin layer of a Si nitride (or oxynitride) on the Si which serves as a barrier to oxida-tion; the nitride is believed to occur as a result of N I ~ generation f r o m the masking Si3N4 during isolation oxidation followed by interaction of the NHa w i t h the Si substrate (2).…”

mentioning

confidence: 99%

“…The thinning of the gate oxide has been attributed to the presence of a thin layer of a Si nitride (or oxynitride) on the Si which serves as a barrier to oxida-tion; the nitride is believed to occur as a result of N I ~ generation f r o m the masking Si3N4 during isolation oxidation followed by interaction of the NHa w i t h the Si substrate (2). One processing procedure that has been introduced in an a t t e m p t to minimize the f r e q u e n c y of occurrence or magnitude of this anomalous thinning is the use of an additional Si3N4 etch (4). A f t e r the isolation oxide is grown, the masking oxide or oxynitride over the Si3N4, the Si3N4, and the underlying oxide layer (called the "pad oxide") are r e m o v e d by BHF, hot HePO4, and BHF, respectively.…”

mentioning

confidence: 99%

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Bird's Beak Configuration and Elimination of Gate Oxide Thinning Produced during Selective Oxidation

Shankoff¹,

Sheng²,

Haszko³

et al. 1980

J. Electrochem. Soc.

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In the selective oxidation scheme for processing Si MOS devices, Si3N4 is used to mask gate oxide areas against the isolation oxidation. After removing the Si3N4 , gate oxide is grown. This scheme produces three topographical features which have ramifications in subsequent processing and in device properties: a notch in the isolation oxide, penetration of the isolation oxide under the masking Si3N4 , and thinning of the gate oxide at the isolation oxide edge; the first two features form the bird's beak configuration. The transmission electron microscope was applied to thin film (<1 μm) cross sections through the bird's beak in order to obtain an accurate description of these features. The bird's beak extended typically 1.5 and 0.8 μm in the n‐ and p‐channel structures, respectively, leading to a corresponding decrease in the active device length of 3.8 and 2.3 μm for the 1.4 μm thick isolation oxide. Gate oxide at the edge of the bird's beak was thinned 35–100% in the n‐channel samples and 20–50% in the p‐channel samples. It was found that oxidation subsequent to the isolation oxidation and Si3N4 removal destroys the oxidation barrier (wet oxidation seemingly more effective than dry and more convenient). Thus, a method which incorporates an additional, short, sacrificial wet oxidation step between isolation and gate oxidations, in order to overcome the thinning phenomenon, is described.

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Section: Applications Of Electrochemical Methods Formentioning

confidence: 99%

mentioning

confidence: 99%

mentioning

confidence: 99%

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Bird's Beak Configuration and Elimination of Gate Oxide Thinning Produced during Selective Oxidation

Shankoff¹,

Sheng²,

Haszko³

et al. 1980

J. Electrochem. Soc.

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“…The polysilicon regions may serve as an FET gate, a capacitor plate, an interconnection line, or a contact area. Then an insulation oxide is thermally grown and/or deposited over the structure [10]. The third masking pattern defines contact vias to source, drain, and polysilicon areas.…”

Section: Self-registering Contact Techniquementioning

confidence: 99%

A One-Device Memory Cell Using a Single Layer of Polysilicon and a Self-Registering Metal-to-Polysilicon Contact

1980

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The fabrication and operation of a novel one-device dynamic memory cell are described. Like the conventional double overlapping polysilicon cell, the new memory cell has a dijfused bit line and a metal word line, uses five basic masking operations, and provides essentially equivalent cell area for the same lithographic feature size. Unlike the double polysilicon cell, however, the new cell uses a single layer of polysilicon to provide a more planar surface topography, and a self-registering metal-to-poly silicon contact to provide a small cell area. An essential aspect of the fabrication method of the self-registered contact cell is the use of two lithographic masking operations that define two patterns in a single polysilicon layer, the MOSFET gate electrode and the MOS capacitor electrode. The self-registering contact also facilitates a powerful polysilicon wiring technique that is applicable to the access circuits located peripherally to the array of memory cells.

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Insulated Gate Field-Effect-Transistors: MOSFETs, IGFETs and Related Devices

Milnes

1980

Semiconductor Devices and Integrated Electronics

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An n-channel Si-gate integrated circuit technology

Cited by 7 publications

References 0 publications

Bird's Beak Configuration and Elimination of Gate Oxide Thinning Produced during Selective Oxidation

Bird's Beak Configuration and Elimination of Gate Oxide Thinning Produced during Selective Oxidation

A One-Device Memory Cell Using a Single Layer of Polysilicon and a Self-Registering Metal-to-Polysilicon Contact

Insulated Gate Field-Effect-Transistors: MOSFETs, IGFETs and Related Devices

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