An on-chip 3MB subarray-based 3rd level cache on an itanium microprocessor

Weiss, D.; Wuu, John; Chin, V.

doi:10.1109/isscc.2002.992132

Cited by 9 publications

(10 citation statements)

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“…Unfortunately, this is not representative of modern designs, since cache wave-pipelining is not being used by contemporary microprocessors [21,24]. Although wave pipelining has been shown to work in silicon prototypes [4], it is not ideally suited for high-speed microprocessor caches targeted for volume production which have to operate with significant process-voltage-temperature (PVT) variations.…”

Section: Pipelined Cachesmentioning

confidence: 99%

Energy/power breakdown of pipelined nanometer caches (90nm/65nm/45nm/32nm)

Rodríguez

Jacob

2006

Proceedings of the 2006 International Symposium on Low Power Electronics and Design - ISLPED '06

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As transistors continue to scale down into the nanometer regime, device leakage currents are becoming the dominant cause of power dissipation in nanometer caches, making it essential to model these leakage effects properly. Moreover, typical microprocessor caches are pipelined to keep up with the speed of the processor, and the effects of pipelining overhead need to be properly accounted for.In this paper, we present a detailed study of pipelined nanometer caches with detailed energy/power dissipation breakdowns showing where and how the power is dissipated within a nanometer cache. We explore a three-dimensional pipelined cache design space that includes cache size (16kB to 512kB), cache associativity (directmapped to 16-way) and process technology (90nm, 65nm, 45nm and 32nm).Among our findings, we show that cache bitline leakage is increasingly becoming the dominant cause of power dissipation in nanometer technology nodes. We show that subthreshold leakage is the main cause of static power dissipation, and that gate leakage is, surprisingly, not a significant contributor to total cache power, even for 32nm caches. We also show that accounting for cache pipelining overhead is necessary, as power dissipated by the pipeline elements is a significant part of cache power.

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Section: Pipelined Cachesmentioning

confidence: 99%

Energy/power breakdown of pipelined nanometer caches (90nm/65nm/45nm/32nm)

Rodríguez

Jacob

2006

Proceedings of the 2006 International Symposium on Low Power Electronics and Design - ISLPED '06

View full text Add to dashboard Cite

show abstract

“…Unfortunately, this is not representative of modem designs, since cache wave-pipelining is not being used by contemporary microprocessors [21,24]. Although wave pipelining has been shown to work in silicon prototypes [4], it is not ideally suited for high-speed microprocessor caches targeted for volume production which have to operate with significant process-voltage-temperature (PVT) variations.…”

Section: Pipelined Cachesmentioning

confidence: 99%

Energy/Power Breakdown of Pipelined Nanometer Caches (90nm/65nm/45nm/32nm)

Rodríguez¹,

Jacob²

2006

ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design

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As transistors continue to scale down into the nanometer regime, device leakage currents are becoming the dominant cause of power dissipation in nanometer caches, making it essential to model these leakage effects properly. Moreover, typical microprocessor caches are pipelined to keep up with the speed of the processor, and the effects ofpipelining overhead need to be properly accounted for.In this paper, we present a detailed study of pipelined nanometer caches with detailed energy/power dissipation breakdowns showing where and how the power is dissipated within a nanometer cache. We explore a three-dimensional pipelined cache design space that includes cache size (16kB to 512kB), cache associativity (directmapped to 16-way) and process technology (9Onm, 65nrn, 45nm and 32nm).Among our findings, we show that cache bitline leakage is increasingly becoming the dominant cause of power dissipation in nanometer technology nodes. We show that subthreshold leakage is the main cause of static power dissipation, and that gate leakage is, surprisingly, not a significant contributor to total cache power, even for 32nm caches. We also show that accounting for cache pipelining overhead is necessary, as power dissipated by the pipeline elements is a significant part ofcache power.

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“…In embedded RAMs (e-RAMs), recent developments have focused on high speed under low voltages, exemplified by the 1.5-V, 300-MHz, 16-Mb DRAM macro [5] and the 1.5-V, 1-GHz, 24-Mb L3-SRAM cache [6]. Device miniaturization and the rapidly growing demand for mobile or power-aware systems have resulted in an urgent need to reduce power-supply voltage (V CC ) ( Figure 2).…”

Section: Introductionmentioning

confidence: 99%

Review and future prospects of low-voltage RAM circuits

et al. 2003

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This paper describes low-voltage random-access memory (RAM) cells and peripheral circuits for standalone and embedded RAMs, focusing on stable operation and reduced subthreshold current in standby and active modes. First, technology trends in low-voltage dynamic RAMs (DRAMs) and static RAMs (SRAMs) are reviewed and the challenges of lowvoltage RAMs in terms of cell signal charge are clarified, including the necessary threshold voltage, V T , and its variations in the MOS field-effect transistors (MOSFETs) of RAM cells and sense amplifiers, leakage currents (subthreshold current and gate-tunnel current), and speed variations resulting from design parameter variations. Second, developments in conventional RAM cells and emerging cells, such as DRAM gain cells and leakage-immune SRAM cells, are discussed from the viewpoints of cell area, operating voltage, and leakage currents of MOSFETs. Third, the concepts proposed to date to reduce subthreshold current and the advantages of RAMs with respect to reducing the subthreshold current are summarized, including their applications to RAM circuits to reduce the current in standby and active modes, exemplified by DRAMs. After this, design issues in other peripheral circuits, such as sense amplifiers and low-voltage supporting circuits, are discussed, as are power management to suppress speed variations and reduce the power of power-aware systems, and testing. Finally, future prospects based on the above discussion are examined.

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An on-chip 3MB subarray-based 3rd level cache on an itanium microprocessor

Abstract: This 3MB on-chip level-three cache employs subarray design style, and achieves 85% array efficiency. Characterized to operate up to 1 2GHz, the cache allows a store and a load in every four core cycles, and provides a total bandwidth of 64GB/s at 1 .OGHz. J. Wuu

Cited by 9 publications

References 0 publications

Energy/power breakdown of pipelined nanometer caches (90nm/65nm/45nm/32nm)

Energy/power breakdown of pipelined nanometer caches (90nm/65nm/45nm/32nm)

Energy/Power Breakdown of Pipelined Nanometer Caches (90nm/65nm/45nm/32nm)

Review and future prospects of low-voltage RAM circuits

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