An Open Framework for Rapid Prototyping of Signal Processing Applications

Pelcat, Maxime; Piat, Jonathan; Wipliez, Matthieu; Aridhi, Slaheddine; Nezan, Jean-François

doi:10.1155/2009/598529

Cited by 42 publications

(31 citation statements)

References 16 publications

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“…The memory bounds are computed in the PREESM 1 rapid prototyping framework [7]. PREESM is an open-source Eclipse-based tool providing graph transformation algorithms, multi-core scheduling and C code generation from IBSDF graphs.…”

Section: Resultsmentioning

confidence: 99%

“…It allows the system designer to discard architectures with insufficient memory and to evaluate the degree of memory optimization required to produce the final system with an optimal amount of memory. Figure 3 illustrates the position of the memory bounds computation in the rapid prototyping process as proposed in [7]. Rapid prototyping inputs consist of an algorithm model respecting the IBSDF MoC, an architecture model respecting the System-Level Architecture Model (S-LAM) semantics [8] and a scenario providing constraints and prototyping parameters.…”

Section: B Hardware/software Exploration Workflowmentioning

confidence: 99%

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Memory bounds for the distributed execution of a hierarchical Synchronous Data-Flow graph

Desnos

Pelcat

Nezan

et al. 2012

2012 International Conference on Embedded Computer Systems (SAMOS)

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Abstract-This paper presents an application analysis technique to define the boundary of shared memory requirements of Multiprocessor System-on-Chip (MPSoC) in early stages of development. This technique is part of a rapid prototyping process and is based on the analysis of a hierarchical Synchronous Data-Flow (SDF) graph description of the system application. The analysis does not require any knowledge of the system architecture, the mapping or the scheduling of the system application tasks.The initial step of the method consists of applying a set of transformations to the SDF graph so as to reveal its memory characteristics. These transformations produce a weighted graph that represents the different memory objects of the application as well as the memory allocation constraints due to their relationships. The memory boundaries are then derived from this weighted graph using analogous graph theory problems, in particular the Maximum-Weight Clique (MWC) problem. Stateof-the-art algorithms to solve these problems are presented and a heuristic approach is proposed to provide a near-optimal solution of the MWC problem. A performance evaluation of the heuristic approach is presented, and is based on hierarchical SDF graphs of realistic applications. This evaluation shows the efficiency of proposed heuristic approach in finding near optimal solutions.

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Section: Resultsmentioning

confidence: 99%

Section: B Hardware/software Exploration Workflowmentioning

confidence: 99%

Memory bounds for the distributed execution of a hierarchical Synchronous Data-Flow graph

Desnos

Pelcat

Nezan

et al. 2012

2012 International Conference on Embedded Computer Systems (SAMOS)

Self Cite

View full text Add to dashboard Cite

show abstract

“…This tool however has some limitations: it is not open source and it has its own model of computation which does not allow schedulability analysis. To overcome these limits, Pelcat et al reimplemented AAA in Preesm [6]. This tool can start its analysis from algorithms described by means of Synchronous Data Flow graphs, but these are transformed into Homogeneous SDF and then in Directed Acyclic Graph before computing scheduling.…”

Section: Related Workmentioning

confidence: 99%

“…The analyses performed by considering this information in a separate way (i.e., without embedding it into the SDF graph) are possible, but can be much more complex. For examples, approaches like the ones presented in [6] and [7] require to transform the analyzed SDF graph in a Homogeneous SDF, potentially increasing in a very significant way the size of the graph to be analyzed and so the complexity of the rest of the flow [11].…”

Section: Modeling Resolution Of Resources Contentionmentioning

confidence: 99%

Modeling Resolution of Resources Contention in Synchronous Data Flow Graphs

Lattuada

Ferrandi

2014

J Sign Process Syst

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Synchronous Data Flow graphs are widely adopted in the designing of streaming applications, but were originally formulated to describe only how an application is partitioned and which data are exchanged among different tasks. Since Synchronous Data Flow graphs are often used to describe and evaluate complete design solutions, missing information (e.g., mapping, scheduling, etc.) has to be included in them by means of further actors and channels to obtain accurate evaluations. To address this issue preserving the simplicity of the representation, techniques that model data transfer delays by means of ad-hoc actors have been proposed, but they model independently each communication ignoring contentions. Moreover, they do not usually consider at all delays due to buffer contentions, potentially overestimating the throughput of a design solution.In this paper a technique to extend Synchronous Data Flow graphs by adding ad-hoc actors and channels to model resolution of resources contentions is proposed. The results show that the number of added actors and channels is limited but that they can significantly increase the Synchronous Data Flow graph accuracy.

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“…Ptolemy [13] shows the importance of using higher-level representation constructs to build real-time functionality. Pelcat et al [14] present an open-source Eclipse-based framework, which aims to facilitate the exploration and development processes in this context.…”

Section: Introductionmentioning

confidence: 99%

Internet-based hardware/software co-design framework for embedded 3D graphics applications

Yeh

Wang

Huang

et al. 2011

EURASIP J. Adv. Signal Process.

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Advances in technology are making it possible to run three-dimensional (3D) graphics applications on embedded and handheld devices. In this article, we propose a hardware/software co-design environment for 3D graphics application development that includes the 3D graphics software, OpenGL ES application programming interface (API), device driver, and 3D graphics hardware simulators. We developed a 3D graphics system-on-a-chip (SoC) accelerator using transaction-level modeling (TLM). This gives software designers early access to the hardware even before it is ready. On the other hand, hardware designers also stand to gain from the more complex test benches made available in the software for verification. A unique aspect of our framework is that it allows hardware and software designers from geographically dispersed areas to cooperate and work on the same framework. Designs can be entered and executed from anywhere in the world without full access to the entire framework, which may include proprietary components. This results in controlled and secure transparency and reproducibility, granting leveled access to users of various roles.

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An Open Framework for Rapid Prototyping of Signal Processing Applications

Cited by 42 publications

References 16 publications

Memory bounds for the distributed execution of a hierarchical Synchronous Data-Flow graph

Memory bounds for the distributed execution of a hierarchical Synchronous Data-Flow graph

Modeling Resolution of Resources Contention in Synchronous Data Flow Graphs

Internet-based hardware/software co-design framework for embedded 3D graphics applications

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