An open-source HyperTransport core

Slogsnat, David; Giese, Alexander; Nüssle, Mondrian; Brüning, Ulrich

doi:10.1145/1391732.1391734

Cited by 25 publications

(9 citation statements)

References 6 publications

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“…The HTX FPGA board has a Xilinx Virtex4-100 FPGA device. For the FPGA interface with the HyperTransport bus we used the HTX module developed in [23] which supports 3.2 GBytes/sec throughput (unidirectional, 16-bit link width). The HTX interface allows data transfers of 32 to 512 bit data while command packets are 96-bits.…”

Section: Resultsmentioning

confidence: 99%

General Purpose Computing with Reconfigurable Acceleration

Brandon

Sourdis

Gaydadjiev

2010

2010 International Conference on Field Programmable Logic and Applications

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In this thesis we describe a new generic approach for accelerating software functions using a reconfigurable device connected through a high-speed link to a general purpose system. In order for our solution to be generic, as opposed to related ISA extension approaches, we insert system calls into the original program to control the reconfigurable accelerator using a compiler plug-in. We define specific mechanisms for the communication between the reconfigurable device, the host general purpose processor and the main memory. The reconfigurable device is controlled by the host through system calls provided by the device driver, and initiates communication by raising interrupts; it further has direct accesses to the main memory (DMA) operating in the virtual address space. To do so, the reconfigurable device supports address translation, while the driver serves the device interrupts, ensures that shared data in the host-cache remain coherent, and handles memory protection and paging. The system is implemented using a machine which provides a HyperTransport bus connecting a Xilinx Virtex4-100 FPGA to the host. We evaluate alternative design choices of our proposal using an AES application and accelerating its most computationally intensive function. Our experimental results show that our solution is up to 5× faster than software and achieves a processing throughput equal to the theoretical maximum. n this thesis we describe a new generic approach for accelerating software functions using a reconfigurable device connected through a high-speed link to a general purpose system. In order for our solution to be generic, as opposed to related ISA extension approaches, we insert system calls into the original program to control the reconfigurable accelerator using a compiler plug-in. We define specific mechanisms for the communication between the reconfigurable device, the host general purpose processor and the main memory. The reconfigurable device is controlled by the host through system calls provided by the device driver, and initiates communication by raising interrupts; it further has direct accesses to the main memory (DMA) operating in the virtual address space. To do so, the reconfigurable device supports address translation, while the driver serves the device interrupts, ensures that shared data in the host-cache remain coherent, and handles memory protection and paging. The system is implemented using a machine which provides a HyperTransport bus connecting a Xilinx Virtex4-100 FPGA to the host. We evaluate alternative design choices of our proposal using an AES application and accelerating its most computationally intensive function. Our experimental results show that our solution is up to 5× faster than software and achieves a processing throughput equal to the theoretical maximum. Laboratory: Computer Engineering Codenumber : CE-MS

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Section: Resultsmentioning

confidence: 99%

General Purpose Computing with Reconfigurable Acceleration

Brandon

Sourdis

Gaydadjiev

2010

2010 International Conference on Field Programmable Logic and Applications

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“…Regarding the 3 Note that these times are reported as full-round trip latency, in opposite to message passing latencies which are usually reported as halfround trip latencies. For a comparison these times should therefore be divided by two.…”

Section: Discussionmentioning

confidence: 99%

“…Due to this, HyperTransport (HT) [3] is used as the interface between the communication engine and the host system. HT allows a direct connection between communication engine and host CPUs and memory controllers, avoiding any kind of protocol conversion or intermediate bridges.…”

Section: Prototypingmentioning

confidence: 99%

Efficient hardware support for the Partitioned Global Address Space

Fröning

Litz

2010

2010 IEEE International Symposium on Parallel &Amp; Distributed Processing, Workshops and PHD Forum (IPDPSW)

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We present a novel architecture of a communication engine for non-coherent distributed shared memory systems. The shared memory is composed by a set of nodes exporting their memory. Remote memory access is possible by forwarding local load or store transactions to remote nodes. No software layers are involved in a remote access, neither on origin or target side: a user level process can directly access remote locations without any kind of software involvement. We have implemented the architecture as an FPGA-based prototype in order to demonstrate the functionality of the complete system. This prototype also allows real world measurements in order to show the performance potential of this architecture, in particular for fine grain memory accesses like they are typically used for synchronization tasks.

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“…In order to implement the RMC, we are leveraging the HTX card designed by University of Heidelberg [29][21] [22]. This card, shown in Figure 10, contains an FPGA where we load several IP blocks also developed by the mentioned university, comprising the Open-Source HyperTransport Core [38], a router for communication among nodes, and the RMC functionality. This prototype will serve as a demonstrator for our proposal.…”

Section: Prototyping the New Architecturementioning

confidence: 99%

A new degree of freedom for memory allocation in clusters

et al. 2011

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Fröning, H.; Duato Marín, JF. (2012). A new degree of freedom for memory allocation in clusters. Cluster Computing. 15(2):101-123. doi:10.1007/s10586-010-0150-7.Noname manuscript No. (will be inserted by the editor) A New Degree of Freedom for Memory Allocation in ClustersHéctor Montaner · Federico Silla · Holger Fröning · José DuatoReceived: date / Accepted: date Abstract Improvements in parallel computing hardware usually involve increments in the number of available resources for a given application such as the number of computing cores and the amount of memory. In the case of shared-memory computers, the increase in computing resources and available memory is usually constrained by the coherency protocol, whose overhead rises with system size, limiting the scalability of the final system. In this paper we propose an efficient and cost-effective way to increase the memory available for a given application by leveraging free memory in other computers in the cluster.Our proposal is based on the observation that many applications benefit from having more memory resources but do not require more computing cores, thus reducing the requirements for cache coherency and allowing a simpler implementation and better scalability.Simulation results show that, when additional mechanisms intended to hide remote memory latency are used, execution time of applications that use our proposal is similar to the time required to execute them in a computer populated with enough local memory, thus validating the feasibility of our proposal. We are currently building a prototype that implements our ideas. The first results from real executions in this prototype demonstrate not only that our proposal works but also that it can efficiently execute applications that make use of remote memory resources.

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An open-source HyperTransport core

Cited by 25 publications

References 6 publications

General Purpose Computing with Reconfigurable Acceleration

General Purpose Computing with Reconfigurable Acceleration

Efficient hardware support for the Partitioned Global Address Space

A new degree of freedom for memory allocation in clusters

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