An Optimized p⁺Shielding 4H-SiC Trench Gate MOSFETs Structure with Floating Regions

Abstract

In this paper, an optimized p+ shielding 4H-SiC trench-gate metal-oxide-semiconductor field effect transistors (UMOSFETs) structure with floating regions is proposed. The p+ shielding region is moved down to gain a low device on-resistance and the floating regions are designed to improve the breakdown voltage in the proposed structure. Specific on-resistances of the proposed 4H-SiC UMOSFETs is 2.62 mΩ.cm2 at VGS=18 V and VDS=10 V, compared with 4.77 mΩ.cm2 for the conventional p+ shielding UMOSFETs structure with same breakdown voltage. The on-resistance and figure of merit (FOM = VBR2/Ron) improve by 45.1% and 94.2%, respectively.