In this paper, SiC MOS capacitors were fabricated and annealed in Ar/O2 = 9:1 ambient with different temperature, and the annealing effects on the reliability and performance of SiC MOS capacitance were investigated. We found that annealing in Ar/O2 ambient is capable to improve the reliability of gate oxide. When annealing in higher temperature, defects near SiO2/SiC interface are reduced, but the gate reliability deteriorated. It is difficult to obtain the best performance and reliability under the same conditions. There is a trade-off between Dit and reliability to adjust the annealing conditions.

A novel process is developed for minority carrier lifetime enhancement in ultra-high 4H-SiC PiN diodes. It comprises two separate processes. Firstly, the ultra-thick epitaxial grown drift layer (200μm) covered with a protective thin carbon film is subject to a 1500°C high-temperature anneal process in Ar atmosphere for 2 hours. Secondly, a surface passivation process is adopted to reduce the surface recombination rate. μ-PCD tests show that after high-temperature anneal, the thick drift layer shows a minority carrier lifetime increase to about 1.6 μs. PiN diodes based on the novel process are fabricated and their electric characteristics are measured. Results show a low specific on-resistance of 16.3 mΩ·cm2 at 25°C and 14 mΩ·cm2 at 125 °C. Compared with simulation results, it is shown that its effective minority carrier lifetime increase to about 5μs .Our study demonstrates that the developed novel process is effective in minority carrier lifetime enhancement in ultra-voltage 4H-SiC PiN diodes.

LaxHfyO nanolaminated thin film deposited using atomic layer deposition process has been studied as a high-K gate dielectric in 4H-SiC MOS capacitors. The electrical and nano-laminated film characteristics were studied with increasing post deposition annealing (PDA) in N2O ambient. The result shows that high quality LaxHfyO nano-laminated thin films with good interface and bulk qualities are fabricated using high PDA temperature.

The effect of the field oxidation process on the electrical characteristics of 6500V 4H-SiC JBS diodes is studied. The oxide thickness and field plate length have an effect on the reverse breakdown voltage of the SiC JBS diode. According the simulation results, we choose the optimal thickness of the oxide layer and field plate length of the SiC JBS diode. Two different field oxide deposition processes, which are plasma enhanced chemical vapor deposition (PECVD) and low pressure chemical vapor deposition (LPCVD), are compared in our paper. When the reverse voltage is 6600V, the reverse leakage current of SiC JBS diodes with the field oxide layer obtained by LPCVD process is 0.7 μA, which is 60% lower than that of PECVD process. When the forward current is 25 A, the forward voltage of SiC JBS diodes with the field oxide layer obtained by LPCVD process is 3.75 V, which is 10% higher than that of PECVD process. There should be a trade-off between the forward and reverse characteristics in the actual high power and high temperature applications.

In this paper, an optimized p+ shielding 4H-SiC trench-gate metal-oxide-semiconductor field effect transistors (UMOSFETs) structure with floating regions is proposed. The p+ shielding region is moved down to gain a low device on-resistance and the floating regions are designed to improve the breakdown voltage in the proposed structure. Specific on-resistances of the proposed 4H-SiC UMOSFETs is 2.62 mΩ.cm2 at VGS=18 V and VDS=10 V, compared with 4.77 mΩ.cm2 for the conventional p+ shielding UMOSFETs structure with same breakdown voltage. The on-resistance and figure of merit (FOM = VBR2/Ron) improve by 45.1% and 94.2%, respectively.