An Output Buffer for 3.3-V Applications in a 0.13-$\mu$m 1/2.5-V CMOS Process

Chen, S.; Ker, Ming Dou

doi:10.1109/tcsii.2006.884118

Cited by 4 publications

(5 citation statements)

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Section: Problem Definitionmentioning

confidence: 99%

High speed stress tolerant 1.6 V – 3.6 V low to high voltage CMOS level shift architecture in 40 nm

Monga

2012

2012 IEEE International Symposium on Circuits and Systems

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An architecture for the scalable speed and multiple supply voltage range of 1.6 V to 3.6 V, low voltage to high voltage level shifter has been proposed. The buffer containing the level shifter is fabricated in 40 nm CMOS process by thin oxide (32Å thick) devices whose stress limit is 1.98 V (max). The technique generates a set of dynamic differential bias signals as a function of input data sequence, output state of the level shifter and the supply voltage for a given process and temperature to ensure the reliable operation of the level shift stage. The measurement results confirmed successful operation at 40 Mbps with 10 pF load on IO pad, with multiple supplies, 1.8 V -2.7 V -3.6 V.

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Section: Problem Definitionmentioning

confidence: 99%

High speed stress tolerant 1.6 V – 3.6 V low to high voltage CMOS level shift architecture in 40 nm

Monga

2012

2012 IEEE International Symposium on Circuits and Systems

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“…Therefore, buffers (namely, level converter) for the chips fabricated by the advanced processes to accommodate high or low voltage swings from "older" circuits are needed in such a scenario, as shown in Fig. 1 [1][2][3][4][5][6][7][8][9][10][11]. Notably, these buffer will occupy a significant portion of the PCB.…”

Section: Introductionmentioning

confidence: 99%

Process corner detection by skew inverters for 500 MHZ 2×VDD output buffer using 40-nm CMOS technology

Wang

Juan

et al. 2015

Microelectronics Journal

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“…In transmit mode, according to the above analysis, the gate-controlled circuit biases the gate voltages TP and TN of transistors MP and MN at VDD, and then the dynamic source output stage controls the transistors MP and MN to be on or off by changing their source voltages. When the I/O buffer transmits 2xVDD output signal, PUH is pulled down to VDD by the level converter which is implemented with all 1xVDD devices [8]. Then, the voltage at node A is 2xVDD due to the conduction of transistor MPP while MPN is off.…”

Section: Introductionmentioning

confidence: 99%

Design of 2xVDD-tolerant I/O buffer with 1xVDD CMOS devices

Ker

Lin

2009

2009 IEEE Custom Integrated Circuits Conference

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A new 2xVDD-tolerant I/O buffer realized with only 1xVDD devices has been proposed and verified in a 0.18-µm CMOS process. With the dynamic source output technique and the new gate-controlled circuit, the new proposed I/O buffer can transmit and receive the signals with the voltage swing twice as high as the normal power supply voltage (VDD) without suffering gate-oxide reliability problem. The proposed 2xVDD-tolerant I/O circuit solution can be implemented in different nanoscale CMOS processes to meet the mixed-voltage interface applications in microelectronic systems.

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An Output Buffer for 3.3-V Applications in a 0.13-$\mu$m 1/2.5-V CMOS Process

Cited by 4 publications

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High speed stress tolerant 1.6 V – 3.6 V low to high voltage CMOS level shift architecture in 40 nm

High speed stress tolerant 1.6 V – 3.6 V low to high voltage CMOS level shift architecture in 40 nm

Process corner detection by skew inverters for 500 MHZ 2×VDD output buffer using 40-nm CMOS technology

Design of 2xVDD-tolerant I/O buffer with 1xVDD CMOS devices

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An Output Buffer for 3.3-V Applications in a 0.13-$\mu$m 1/2.5-V CMOS Process

Cited by 4 publications

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High speed stress tolerant 1.6 V &#x2013; 3.6 V low to high voltage CMOS level shift architecture in 40 nm

High speed stress tolerant 1.6 V &#x2013; 3.6 V low to high voltage CMOS level shift architecture in 40 nm

Process corner detection by skew inverters for 500 MHZ 2×VDD output buffer using 40-nm CMOS technology

Design of 2xVDD-tolerant I/O buffer with 1xVDD CMOS devices

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High speed stress tolerant 1.6 V – 3.6 V low to high voltage CMOS level shift architecture in 40 nm

High speed stress tolerant 1.6 V – 3.6 V low to high voltage CMOS level shift architecture in 40 nm