An output structure for a bi-modal 6.4-Gbps GDDR5 and 2.4-Gbps DDR3 compatible memory interface

Mishra, N.; Jain, Manish; Le, Phuong; Mukherjee, S.; Sendhil, Arul; Amirkhany, Amir

doi:10.1109/cicc.2011.6055399

Cited by 3 publications

(1 citation statement)

References 3 publications

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“…While K20M uses a state-of-the-art GDDR5 memory manufactured at a 55nm process, DianNao is plugged to a DDR3 memory at a 80nm process. Even at the same process, GDDR5 is still 2.39x more energy-efficient than DDR3 [20]. Therefore, it can be expected that the energy reduction of DianNao over the GPU will significantly increase when using similar main memory.…”

Section: Energymentioning

confidence: 95%

A High-Throughput Neural Network Accelerator

Du¹,

Sun²,

Wang³

et al. 2015

IEEE Micro

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Machine-Learning tasks are becoming pervasive in a broad range of domains, and in a broad range of systems (from embedded systems to data centers). Recent advances on machine-learning show that neural networks are the state-of-the-art across many applications. As architectures evolve towards heterogeneous multi-cores composed of a mix of cores and accelerators, a neural network accelerator can achieve the rare combination of efficiency (due to the small number of target algorithms) and broad application scope.Until now, most machine-learning accelerator designs have been focusing on efficiently implementing the computational part of the algorithms. However, recent state-of-the-art neural networks are characterized by their large size. In this study, we design an accelerator architecture for large-scale neural networks, with a special emphasis on the impact of memory on accelerator design, performance and energy. We present a concrete design at 65nm which can perform 496 16-bit fixed-point operations in parallel every 1.02ns, i.e., 452 GOP/s, in a 3.02mm 2 , 485mW footprint (excluding main memory accesses).

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Section: Energymentioning

confidence: 95%