An overview of flash architectural developments

Campardo, G.; Scotti, M.; Scommegna, S.; Pollara, S.; Silvagni, Andrea

doi:10.1109/jproc.2003.811705

Cited by 19 publications

(4 citation statements)

References 31 publications

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“…Cells store data in floating gate transistors through electron tunneling, and all cells connected to a given word line comprise a page within a block. All cells in a page are operated on together and typically allow for 512 bytes + 16 spare bytes, 2048 bytes + 64 spare bytes, or 4096 bytes + 128 spare bytes of storage in the page [32]. A memory block often contains either 32 or 64 pages.…”

Section: D Nand Flashmentioning

confidence: 99%

Flash-Based Security Primitives: Evolution, Challenges and Future Directions

et al. 2021

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Over the last two decades, hardware security has gained increasing attention in academia and industry. Flash memory has been given a spotlight in recent years, with the question of whether or not it can prove useful in a security role. Because of inherent process variation in the characteristics of flash memory modules, they can provide a unique fingerprint for a device and have thus been proposed as locations for hardware security primitives. These primitives include physical unclonable functions (PUFs), true random number generators (TRNGs), and integrated circuit (IC) counterfeit detection. In this paper, we evaluate the efficacy of flash memory-based security primitives and categorize them based on the process variations they exploit, as well as other features. We also compare and evaluate flash-based security primitives in order to identify drawbacks and essential design considerations. Finally, we describe new directions, challenges of research, and possible security vulnerabilities for flash-based security primitives that we believe would benefit from further exploration.

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Section: D Nand Flashmentioning

confidence: 99%

Flash-Based Security Primitives: Evolution, Challenges and Future Directions

et al. 2021

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“…Two internal Dickson charge pumps (CP) are used [1]: -3.7 V and + 6.8 V to generate high voltages in the memory system for operating the cell. The schematic illustration of the CP circuit is shown in Fig.…”

Section: Device and Experimeantalmentioning

confidence: 99%

“…HV circuits are essential in flash memories to provide high voltages for program and erase operation [1], and are one of the most sensitive building blocks under radiation, leading to write failure after exposure to 20-60 krad(Si) [2]. For radiation hardened flash memories design, it is necessary to understand the origin of the HV circuits' degradation: whether the charge pumps or/and the HV management circuits are degraded.…”

Section: Introductionmentioning

confidence: 99%

Investigation of TID degradation of high voltage circuits in flash memory

Qiao

Pan

Liu

et al. 2013

2013 IEEE International Integrated Reliability Workshop Final Report

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“…This stands in contrast to conventional memory devices or E‐fuses, which typically rely on programming pads or dedicated digital engines. [ 30 , 31 ] The proposed fuse/anti‐fuse method does have the drawback of not enabling real‐time chip programming during active operation and necessitates a relatively slower, serialized post‐fabrication process while methods such as programming through wireless downlink communication can offer quicker alternatives. (We note that there are number of companies developing next generations of laser‐ion‐beam process tools for chip post‐process editing).…”

Section: Introductionmentioning

confidence: 99%

Versatile On‐Chip Programming of Circuit Hardware for Wearable and Implantable Biomedical Microdevices

Lee,

Leung

et al. 2023

Advanced Science

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Wearable and implantable microscale electronic sensors have been developed for a range of biomedical applications. The sensors, typically millimeter size silicon microchips, are sought for multiple sensing functions but are severely constrained by size and power. To address these challenges, a hardware programmable application‐specific integrated circuit design is proposed and post‐process methodology is exemplified by the design of battery‐less wireless microchips. Specifically, both mixed‐signal and radio frequency circuits are designed by incorporating metal fuses and anti‐fuses on the top metal layer to enable programmability of any number of features in hardware of the system‐on‐chip (SoC) designs. This is accomplished in post‐foundry editing by combining laser ablation and focused ion beam processing. The programmability provided by the technique can significantly accelerate the SoC chip development process by enabling the exploration of multiple internal circuit parameters without the requirement of additional programming pads or extra power consumption. As examples, experimental results are described for sub‐millimeter size complementary metal‐oxide‐semiconductor microchips being developed for wireless electroencephalogram sensors and as implantable microstimulators for neural interfaces. The editing technique can be broadly applicable for miniaturized biomedical wearables and implants, opening up new possibilities for their expedited development and adoption in the field of smart healthcare.

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An overview of flash architectural developments

Cited by 19 publications

References 31 publications

Flash-Based Security Primitives: Evolution, Challenges and Future Directions

Flash-Based Security Primitives: Evolution, Challenges and Future Directions

Investigation of TID degradation of high voltage circuits in flash memory

Versatile On‐Chip Programming of Circuit Hardware for Wearable and Implantable Biomedical Microdevices

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