An Overview of Static Pipelining

Finlayson, Ian; Uh, Gang-Ryung; Whalley, David; Tyson, Gary

doi:10.1109/l-ca.2011.26

Cited by 13 publications

(5 citation statements)

References 13 publications

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“…This is the first paper that describes how any SP ToC optimizations are accomplished. With the exception of the SEQ hoisting optimization, all of these optimizations are new as compared to prior SP studies [6][7][8].…”

Section: Sp Transfer Of Control Optimizationsmentioning

confidence: 99%

Optimizing Transfers of Control in the Static Pipeline Architecture

et al. 2015

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Statically pipelined processors offer a new way to improve the performance beyond that of a traditional in-order pipeline while simultaneously reducing energy usage by enabling the compiler to control more fine-grained details of the program execution. This paper describes how a compiler can exploit the features of the static pipeline architecture to apply optimizations on transfers of control that are not possible on a conventional architecture. The optimizations presented in this paper include hoisting the target address calculations for branches, jumps, and calls out of loops, performing branch chaining between calls and jumps, hoisting the setting of return addresses out of loops, and exploiting conditional calls and returns. The benefits of performing these transfer of control optimizations include a 6.8% reduction in execution time and a 3.6% decrease in estimated energy usage.

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Section: Sp Transfer Of Control Optimizationsmentioning

confidence: 99%

Optimizing Transfers of Control in the Static Pipeline Architecture

et al. 2015

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“…The interconnect overhead in TTAs can be reduced by interconnect reduction, which is particularly effective in application specific processor design. Using explicit bypassing is an alternative of building explicit datapath architecture [8,[12][13][14]. The bypassing (forwarding) network in a conventional processors is used to reduce data hazard caused by the pipelining.…”

Section: Processors With Explicit Datapathmentioning

confidence: 99%

A Co-Design Framework with OpenCL Support for Low-Energy Wide SIMD Processor

She

Waeijen

et al. 2014

J Sign Process Syst

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Energy efficiency is one of the most important metrics in embedded processor design. The use of wide SIMD architecture is a promising approach to build energyefficient high performance embedded processors. In this paper, we propose a design framework for a configurable wide SIMD architecture that utilizes an explicit datapath to achieve high energy efficiency. The framework is able to generate processor instances based on architecture specification files. It includes a compiler to efficiently program the proposed architecture with standard programming languages including OpenCL. This compiler can analyze the static memory access patterns in OpenCL kernels, generate efficient mappings, and schedule the code to fully utilize the explicit datapath. Extensive experimental results show that the proposed architecture is efficient and scalable in terms of area, performance, and energy. In a 128-PE SIMD processor, the proposed architecture is able to achieve up to 200 times speed-up and reduce the total energy consumption by 50 % compared to a basic RISC processor.

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“…Finlayson et al [26] show how compiler support can help reducing power consumption without adversely affecting performance when introducing internal registers, that are read and written explicitly, instead of pipeline register. These internal registers reminds a lot of REPLICAs explicit functional unit result registers.…”

Section: Comparison To Previous Workmentioning

confidence: 99%

Code Generation and Global Optimization Techniques for a Reconfigurable PRAM-NUMA Multicore Architecture

Hansson¹

2014

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In this thesis we describe techniques for code generation and global optimization for a PRAM-NUMA multicore architecture. We specifically focus on the REPLICA architecture which is a family massively multithreaded very long instruction word (VLIW) chip multiprocessors with chained functional units that has a reconfigurable emulated shared on-chip memory. The on-ship memory system supports two execution modes, PRAM and NUMA, which can be switched between at run-time.PRAM mode is considered the standard execution mode and targets mainly applications with very high thread level parallelism (TLP). In contrast, NUMA mode is optimized for sequential legacy applications and applications with low amount of TLP. Different versions of the REPLICA architecture have different number of cores, hardware threads and functional units. In order to utilize the REPLICA architecture efficiently we have made several contributionsto the development of a compiler for REPLICA target code generation. It supports both code generation for PRAM mode and NUMA mode and can generate code for different versions of the processor pipeline (i.e. for different numbers of functional units). It includes optimization phases to increase the utilization of the available functional units. We have also contributed to quantitative the evaluation of PRAM and NUMA mode. The results show that PRAM mode often suits programs with irregular memory access patterns and control flow best while NUMA mode suites regular programs better. However, for a particular program it is not always obvious which mode, PRAM or NUMA, will show best performance. To tackle this we contributed a case study for generic stencil computations, using machine learning derived cost models in order to automatically select at runtime which mode to execute in. We extended this to also include a sequence of kernels

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An Overview of Static Pipelining

Cited by 13 publications

References 13 publications

Optimizing Transfers of Control in the Static Pipeline Architecture

Optimizing Transfers of Control in the Static Pipeline Architecture

A Co-Design Framework with OpenCL Support for Low-Energy Wide SIMD Processor

Code Generation and Global Optimization Techniques for a Reconfigurable PRAM-NUMA Multicore Architecture

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