An SRAM Design in 65-nm Technology Node Featuring Read and Write-Assist Circuits to Expand Operating Voltage

Pilo, H.; Barwin, C.; Braceras, G.; Browning, Clyde; Lamphier, S.; Towler, F.

doi:10.1109/jssc.2007.892153

Cited by 103 publications

(42 citation statements)

References 5 publications

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“…However, this technique will only yield a marginal improvement in the write margin; a much more significant improvement can be attained by lowering the supply voltage during write, while maintaining the WL voltage [39]. This is made possible by adopting a long-aspect-ratio cell layout, which is typical in today's designs for better manufacturability [2], [40]- [42], since the cell supply can be routed vertically for each column and can be exploited to break the contention between read and write optimization. With the ability for column-based biasing, cell supply voltage can be selectively lowered only for the column containing the cell under write access [2].…”

Section: B Finfet Sram Cell Designs 1) Conventional Double-gated (Dgmentioning

confidence: 99%

“…This is made possible by adopting a long-aspect-ratio cell layout, which is typical in today's designs for better manufacturability [2], [40]- [42], since the cell supply can be routed vertically for each column and can be exploited to break the contention between read and write optimization. With the ability for column-based biasing, cell supply voltage can be selectively lowered only for the column containing the cell under write access [2]. This keeps the cell stability high for all other cells connected to the same WL.…”

Section: B Finfet Sram Cell Designs 1) Conventional Double-gated (Dgmentioning

confidence: 99%

“…2) Use of assist techniques to enhance read and write margins. Examples of these techniques include the use of lower column supply voltages during write, bitline and wordline bias, pulsed bit lines, read-, and write-assist column circuitry [2], [3]. These techniques aim to increase the array robustness with smaller cells, but necessarily lower array efficiency, resulting in larger area.…”

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confidence: 99%

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SRAM Read/Write Margin Enhancements Using FinFETs

Carlson

Guo

Balasubramanian

et al. 2010

IEEE Trans. VLSI Syst.

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Abstract-Process-induced variations and sub-threshold leakage in bulk-Si technology limit the scaling of SRAM into sub-32 nm nodes. New device architectures are being considered to improve control and reduce short channel effects. Among the likely candidates, FinFETs are the most attractive option because of their good scalability and possibilities for further SRAM performance and yield enhancement through independent gating. The enhancements to read/write margins and yield are investigated in detail for two cell designs employing independently gated FinFETs. It is shown that FinFET-based 6-T SRAM cells designed with pass-gate feedback (PGFB) achieve significant improvements in the cell read stability without area penalty. The write-ability of the cell can be improved through the use of pull-up write gating (PUWG) with a separate write word line (WWL). The benefits of these two approaches are complementary and additive, allowing for simultaneous read and write yield enhancements when the PGFB and PUWG designs are used in combination.

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Section: B Finfet Sram Cell Designs 1) Conventional Double-gated (Dgmentioning

confidence: 99%

Section: B Finfet Sram Cell Designs 1) Conventional Double-gated (Dgmentioning

confidence: 99%

mentioning

confidence: 99%

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SRAM Read/Write Margin Enhancements Using FinFETs

Carlson

Guo

Balasubramanian

et al. 2010

IEEE Trans. VLSI Syst.

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“…Pilo et al directly connect sense amplifiers to every BL pair so that a full-logic level is restored during a read operation. 20 Therefore, bits that have flipped will be written back to the correct data if enough correct signal is generated before data corruption. Cosemans, Dehaene, and Catthoor buffer short local BLs to long global BLs so that the local BLs collapse before the peak cell current, and hence peak cell disturbance, is established.…”

Section: Nho Et Al Have Extended This Static-mentioning

confidence: 99%

Challenges and Directions for Low-Voltage SRAM

Qazi

Sinangil

Chandrakasan

2011

IEEE Des. Test. Comput.

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SRAM IS THE most common embedded-memory option for CMOS ICs. As the supply voltage of lowpower ICs decreases, it must remain compatible with the operating conditions. At the same time, increasingly parallel architectures of such low-power systems demand more on-chip cache to effectively share information across parallel processing units. Finally, supply voltage scaling improves the energy consumed by SRAM and dramatically reduces its leakage power.Achieving low-voltage operation in SRAM faces a confluence of challenges, originating from process variation, and related to bit cell stability, sensing, architecture, and efficient CAD methodologies. The trend toward increased quantity of embedded SRAM in scaled technology compounds the specific need of SRAM in low-power systems. Integrating more memory on chip provides an effective means to use silicon because of memory's lower power density, layout regularity, and performance and power benefits from reduced off-chip bandwidth. As a result, the everincreasing integration of embedded SRAM continues. 2 By employing some of the design innovations discussed in this article, this memory design minimizes energy per access and achieves a 50Â reduction in leakage power by trading off performance. Indeed, low-power systems benefit from SRAMs that function at very low voltage in the state of the art, but such design solutions of lowvoltage SRAM significantly impact area and performance. 3 Reducing this area overhead and further improving the metrics of energy per accessed bit and leakage power will enable new opportunities for low-power electronics in mobile platforms. Wearable electronics, portable medical monitors, and implantable medical devices are some of the applications requiring the storage of significant quantities of information (e.g., patient data), low-access energy caches, and a long operating lifetime from a battery.In this article, we discuss the challenges to embedded-SRAM design, with particular emphasis on the factors that limit the minimum operating supply voltage V min . We also explore various design solutions and discuss open areas of investigation. ChallengesThe workhorse of embedded memory is SRAM based on the 6T (six-transistor) cell, shown in Figure 2a. From this cell, a subarray is assembled by tiling memory cells into a grid with wordlines (WLs) running horizontally and bitlines (BLs) running vertically, as in Figure 3. Each memory cell is associated with one or more WLs and one or more BLs. Nominally, the bit cell supplies and well biases are globally connected to static voltage sources. During read, the WL voltage V WL is raised, and the memory cell discharges either BLT (bitline true) or BLC (bitline complement), depending on the stored data on nodes Q and bQ. A sense amplifier converts the differential signal to a logic-level output. Then, at the end of the read cycle, the BLs return to the positive supply rail. During write, V WL is raised and the BLs are forced to Future Landscape of Embedded MemoriesEditor's note: SRAMs capable of operating a...

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“…An embedded memory that can instead scale in voltage along with logic and share a common supply is thus the most desirable solution. While many techniques have been proposed to achieve this goal, most add considerable complexity to the peripheral circuits of the memory array and result in penalties in performance, power, and area [23]- [25]. Instead, it may be more effective to fundamentally change the circuits or technologies used to build SRAM in order to enable voltage scaling.…”

Section: B Low-voltage Cachesmentioning

confidence: 99%

Practical Strategies for Power-Efficient Computing Technologies

et al. 2010

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| After decades of continuous scaling, further advancement of silicon microelectronics across the entire spectrum of computing applications is today limited by power dissipation. While the trade-off between power and performance is well-recognized, most recent studies focus on the extreme ends of this balance. By concentrating instead on an intermediate range, an $ 8Â improvement in power efficiency can be attained without system performance loss in parallelizable applicationsVthose in which such efficiency is most critical. It is argued that power-efficient hardware is fundamentally limited by voltage scaling, which can be achieved only by blurring the boundaries between devices, circuits, and systems and cannot be realized by addressing any one area alone. By simultaneously considering all three perspectives, the major issues involved in improving power efficiency in light of performance and area constraints are identified. Solutions for the critical elements of a practical computing system are discussed, including the underlying logic device, associated cache memory, off-chip interconnect, and power delivery system. The IBM Blue Gene system is then presented as a case study to exemplify several proposed directions. Going forward, further power reduction may demand radical changes in device technologies and computer architecture; hence, a few such promising methods are briefly considered.

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An SRAM Design in 65-nm Technology Node Featuring Read and Write-Assist Circuits to Expand Operating Voltage

Cited by 103 publications

References 5 publications

SRAM Read/Write Margin Enhancements Using FinFETs

SRAM Read/Write Margin Enhancements Using FinFETs

Challenges and Directions for Low-Voltage SRAM

Practical Strategies for Power-Efficient Computing Technologies

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