An ultra-low energy asynchronous processor for Wireless Sensor Networks

Necchi, L.; Lavagno, Luciano; Pandini, Davide; Vanzago, L.

doi:10.1109/async.2006.9

Cited by 17 publications

(9 citation statements)

References 15 publications

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“…However, they exclude TID and SEL considerations, which are mitigated by RHBD, including SEU. Additionally, asynchronous logic alone has been applied directly in the design of low power wireless sensor nodes [22].…”

Section: Case Study Design and Resultsmentioning

confidence: 99%

Radiation Hardening by Design of Asynchronous Logic for Hostile Environments

Barnhart

Vladimirova

Sweeting

et al. 2009

IEEE J. Solid-State Circuits

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Abstract-A wide range of emerging applications is driving the development of wireless sensor node technology towards a monolithic system-on-a-chip implementation. Of particular interest are hostile environment scenarios where radiation and thermal extremes exist. Radiation hardening by design has been recognized for over a decade as an alternative open-source circuit design approach to mitigate a spectrum of radiation effects, but has significant power and area penalties. Similarly, asynchronous logic design offers potential power savings and performance improvements, with a tradeoff in design complexity and a lesser area penalty. These side effects have prevented wider acceptance of both design approaches. A case study supporting the development of monolithic system-on-a-chip wireless sensor nodes is presented. Synchronous, hardened, and asynchronous/hardened implementations of a textbook microprocessor in 0.35 m austriamicrosystems SiGe BiCMOS technology are compared. The synergy of this novel asynchronous/hardened design approach is confirmed by simulation and hardware results.Index Terms-Asynchronous logic, environmental tolerance, radiation hardening by design, system-on-a-chip.

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Section: Case Study Design and Resultsmentioning

confidence: 99%

Radiation Hardening by Design of Asynchronous Logic for Hostile Environments

Barnhart

Vladimirova

Sweeting

et al. 2009

IEEE J. Solid-State Circuits

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“…However, this assumes that the microcontroller is in sleep state (according to [10]: 51.3 μJ), if nothing must be calculated. The switching time between both states is according to [11] exactly 2 ms, which results in 33 μJ when running the microcontroller at 4 MHz.…”

Section: Communication Aspectmentioning

confidence: 99%

Comparing the Efficiency of Localization Algorithms with the Power-Error-Product (PEP)

Reichenbach

Blumenthal

Timmermann

2008

2008 the 28th International Conference on Distributed Computing Systems Workshops

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The localization process in wireless sensor networks must produce precise positions at minimal requirements. It is hard to comply with these conditions, due to the strong resource limitation of each sensor node. Although numerous algorithms have already been presented, so far there exist neither an extensive simulative comparison of them nor a qualified parameter to indicate their efficiency. Thus, this paper introduces a selected number of the most important algorithms for sensor networks. These algorithms are compared with each other considering achieved localization error and consumed energy. Then, we propose an adequate parameter to quantify their efficiency -the "Power Error Product" (PEP).

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“…Commercial EDA tools and standard cell library are used. But it still uses a custom tool called desync to modify the synchronous netlist [9].…”

Section: Introductionmentioning

confidence: 99%

A De-synchronous Circuit Design Flow using Hybrid Cell Library

Gong

Wang²,

Yong³

et al. 2006

2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings

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Asynchronous circuit dramatically reduces power and electromagnetic emission with respect to synchronous case, and can be easily integrated in a system on a chip (SOC). Desynchronous circuit is a commonly used asynchronous circuit. A de-synchronous circuit design flow is described in this paper. The hybrid cell library, consisting of standard cells and custom cells, is used. The standard cells are used in data path, while custom cells are used in control path. The overall design flow uses commercial EDA tools and is preferable for fast implementation. A 32-bit de-synchronous multiplier is designed and implemented in SMIC 0.35 m process based on this design flow. The comparisons in area, performance and power consumption between de-synchronous and synchronous multipliers are also included.

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An ultra-low energy asynchronous processor for Wireless Sensor Networks

Cited by 17 publications

References 15 publications

Radiation Hardening by Design of Asynchronous Logic for Hostile Environments

Radiation Hardening by Design of Asynchronous Logic for Hostile Environments

Comparing the Efficiency of Localization Algorithms with the Power-Error-Product (PEP)

A De-synchronous Circuit Design Flow using Hybrid Cell Library

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