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Interconnect parasitic effects are one of the limiting factors for the performances of deep submicron VLSI designs, where the interconnect induced delay dominates over the gate delay. Furthermore, as coupling capacitance between wires increases due to the geometry scaling, the design verification process must accurately take into account crosstalk induced effects.In this paper, we describe CASTA (Crosstalk Aware Static Timing Analysis), a new efficient and accurate methodology for the timing performance verification of large VLSI designs, which accurately considers the crosstalk induced delay and noise injection. Our approach is based on the combination of Static Timing Analysis (STA) with interconnect network order reduction macromodeling techniques and it allows to evaluate the crosstalk effects during gate-level delay calculation, thus enlightening potential timing hazards. The timing effects due to the crosstalk between adjacent interconnects are accounted by a order reduction based macromodel of the overall linear interconnect network. The effectiveness of the proposed methodology has been demonstrated with the analysis of the crosstalk effects on a 0.25µm, high density, CMOS technology.

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