Statistical static timing analysis: A survey

Forzan, Cristiano; Pandini, Davide

doi:10.1016/j.vlsi.2008.10.002

Cited by 52 publications

(24 citation statements)

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“…The coefficients are determined by fitting the equation to the data set under the least square criterion. Once the error function is established, the performance function is executed as ( 1) ( )…”

Section: Accuracy Of Interconnect Delay Modelmentioning

confidence: 99%

“…As we are moving towards nanometer technology, variations in process, voltage, and temperature are increasing, causing significant uncertainty in the delay estimation [1] and greatly impacting the yield [2]. As a consequence, various statistical static timing analysis (SSTA) algorithms [3][4][5] have been proposed to compute the statistical variations of timing performance due to the underlying process parameters.…”

Section: Introductionmentioning

confidence: 99%

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Accuracy consideration of a non-Gaussian interconnect delay model for submicron CMOS statistical static timing analysis

Zjajo

Tang

Berkelaar

et al. 2011

The 4th IEEE International NanoElectronics Conference

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In submicron CMOS technology, due to the nonlinearity of the mapping from variation sources to the gate/wire delay, the distribution of the delay is no longer Gaussian. As the widening of process variability calls for accurate non-Gaussian timing models, their deployment requires well-controlled characterization techniques to cope with the complexity and scalability. In this paper, we present a corresponding analysis for the underlying interconnect timing model characterization infrastructure of statistical timing analysis. As the experimental results indicate, the non-Gaussian quadratic interconnect timing model is accurate within 1% error of the corresponding Monte Carlo simulation.

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Section: Accuracy Of Interconnect Delay Modelmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Accuracy consideration of a non-Gaussian interconnect delay model for submicron CMOS statistical static timing analysis

Zjajo

Tang

Berkelaar

et al. 2011

The 4th IEEE International NanoElectronics Conference

View full text Add to dashboard Cite

show abstract

“…Due to process variations, the performance of a manufactured circuit can be upper or lower to the intentionally designed value [2,3]. Process parameter variations define the maximum clock frequency and power consumption that the chip can operate [2,4]. Process variations and the continuous demand for more performance electronic devices and systems have put in struggled the semiconductor industry [5,6].…”

Section: Introductionmentioning

confidence: 99%

Exploring a homotopy approach for the design of nanometer digital circuits tolerant to process variations

Rodríguez

Garcia-Gervacio

Leal

2018

IEICE Electron. Express

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It is known that process parameter variation degrades the performance of nanometer integrated circuits. Process variations reduce the maximum clock frequency operation of the chips. Diverse strategies have been proposed in the literature to overcome this issue, especially optimization algorithms (gate-sizing algorithms). However, convergence related problems have limited their use. In this work, a homotopy approach for the design of nanometer digital circuits tolerant to process variations is proposed. Two optimization strategies are developed in this work, the first based on the homotopy continuation method (HCM) and the second based on a modification of HCM, called in this work reboot homotopy continuation method (RHCM). Three logic paths were implemented to validate the algorithms. The optimization results obtained with the proposed strategies are compared with a Lagrange-Multipliers-based framework. Results obtained from HCM method are equivalent to the obtained with Lagrange Multipliers. On the other side, results obtained from the RHCM method are more accurate than the obtained with HCM and Lagrange Multipliers. Furthermore, the area used to implement the logic paths is lower when RHCM is applied. Moreover, the number of Newton-Rhapson iterations required to find the solutions are lower when RHCM is used; consequently, time computing is also lower.

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“…Taiwan Semiconductor Manufacturing Company (TSMC) has already announced the insertion of transistor-level statistical timing analysis into its reference design flow in order to enhance timing accuracy [2]. There has been intense academic research on statistical timing analysis and timing yield estimation topics especially in the last decade [3,4]. The researchers have to cope with hard problems like modeling inter-and intra-die variations with spatial correlations, accurate delay approximations without solving the actual non-linear and differential delay equations, propagation of the non-Gaussian random variables, etc.…”

Section: Introductionmentioning

confidence: 99%

Stochastic logical effort as a variation aware delay model to estimate timing yield

Bayrakci

2015

Integration

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Statistical static timing analysis: A survey

Cited by 52 publications

References 50 publications

Accuracy consideration of a non-Gaussian interconnect delay model for submicron CMOS statistical static timing analysis

Accuracy consideration of a non-Gaussian interconnect delay model for submicron CMOS statistical static timing analysis

Exploring a homotopy approach for the design of nanometer digital circuits tolerant to process variations

Stochastic logical effort as a variation aware delay model to estimate timing yield

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