An Ultra-Low Power 1.7-2.7 GHz Fractional-N Sub-Sampling Digital Frequency Synthesizer and Modulator for IoT Applications in 40 nm CMOS

Liu, Yao‐Hong; Heuvel, Johan van den; Kuramochi, T.; Barankin, Benjamin; Mateman, Paul; Chillara, Vamshi Krishna; Wang, Bindi; Staszewski, Robert Bogdan; Philips, Kathleen

doi:10.1109/tcsi.2016.2625462

Cited by 54 publications

(37 citation statements)

References 15 publications

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“…Furthermore, if t res is fixed at an integer division of the CKV period T R , then the conventional fine-resolution TDC normalizing multiplier could be greatly simplified or even entirely avoided if that division is a power-of-two integer. After the loop is settled, the calibration starts by observing φ E [k] and correlating it with R R [k] to obtain a gradient ∇ for an LMS adaptation algorithm [3]. This regulates the supply of TDC to maintain its target resolution until the PHE perturbations due to the normalization error are minimized.…”

Section: Proposed Low-voltage Adpll Architecture With Pvt Toleranmentioning

confidence: 99%

“…Traditionally, TDC gain is adjusted via a digital multiplier [5], controlled by an LMS adaptation algorithm [3]. A recent alternative is to maintain a constant TDC inverter delay with a feedback loop by digitally tuning the inverter loading capacitors [10], as shown in Fig.…”

Section: Calibration For Pvt-insensitive Time-to-digital Convertermentioning

confidence: 99%

“…T HE development of radios for Internet of Things (IoT) node devices has spurred research in ultra-lowpower (ULP) all-digital PLLs (ADPLL) performing as local oscillators (LOs) [1]- [3]. The IoT concept entails stringent conditions on the size and weight of battery or other energy storage used to supply the IoT circuitry.…”

Section: Introductionmentioning

confidence: 99%

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A 0.5-V 1.6-mW 2.4-GHz Fractional-N All-Digital PLL for Bluetooth LE With PVT-Insensitive TDC Using Switched-Capacitor Doubler in 28-nm CMOS

Pourmousavian

Kuo

Siriburanon

et al. 2018

IEEE J. Solid-State Circuits

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This paper proposes an ultra-low-voltage (ULV) fractional-N all-digital PLL (ADPLL) powered from a single 0.5-V supply. While its digitally controlled oscillator (DCO) runs directly at 0.5 V, an internal switched-capacitor dc-dc converter "doubles" the supply voltage to all the digital circuitry and particularly regulates the time-to-digital converter (TDC) supply to stabilize its resolution, thus maintaining fixed in-band phase noise (PN) across process, voltage, and temperature (PVT). The ADPLL supports a two-point modulation and forms a Bluetooth low-energy (BLE) transmitter realized in 28-nm CMOS. It maintains in-band PN of −106 dBc/Hz [figure of merit (FoM) of −239.2 dB] and rms jitter of 0.86 ps while dissipating only 1.6 mW at 40-MHz reference. The power consumption reduces to 0.8 mW during the BLE transmission when the DCO switches to open loop. Index Terms-All-digital PLL (ADPLL), Bluetooth low energy (BLE), digitally controlled oscillator (DCO), Internet of Things (IoT), process, voltage, and temperature (PVT) insensitive, regulator, switched-capacitor (SC) dc-dc doubler.

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Section: Proposed Low-voltage Adpll Architecture With Pvt Toleranmentioning

confidence: 99%

Section: Calibration For Pvt-insensitive Time-to-digital Convertermentioning

confidence: 99%

See 1 more Smart Citation

A 0.5-V 1.6-mW 2.4-GHz Fractional-N All-Digital PLL for Bluetooth LE With PVT-Insensitive TDC Using Switched-Capacitor Doubler in 28-nm CMOS

Pourmousavian

Kuo

Siriburanon

et al. 2018

IEEE J. Solid-State Circuits

Self Cite

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“…It is generally based on a Phase-Locked Loop (PLL). These last two decades have witnessed the gradual substitution of the classic analog PLL in favor of the All-Digital PLL (ADPLL) [1][2][3][4]. Indeed, digital phase synthesis techniques offer various advantages.…”

Section: Introductionmentioning

confidence: 99%

A comprehensive in-depth study of tri-state inverter based DCO

Terosiet

Zianbetov²,

Vallette

et al. 2020

Microelectronics Journal

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“…Ring oscillators [11][12][13] have a simple structure and wide tuning range, but their noise performance is weaker than that of LC oscillators. To reach the performance of the counterparts in CPPLLs, i.e., the voltage-controlled oscillators (VCOs), the oscillator in [14] used a nine-bit digital-to-analog converter (DAC) to convert the digital frequency control words (FCW) to analog signals that were fed to a VCO. Although it had a very high resolution, the added DAC multiplied the burdens of power consumption and area.…”

Section: Introductionmentioning

confidence: 99%

A 0.5~0.7 V LC Digitally Controlled Oscillator Based on a Multi-Stage Capacitance Shrinking Technique

Wang

et al. 2019

Electronics

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This paper presents a 2.4 GHz LC digitally controlled oscillator (DCO) at near-threshold supplies (0.5~0.7 V). It was a challenge to achieve a low voltage, low power, and high resolution simultaneously. DCOs with metal oxide semiconductor (MOS) varactors consume low power, but their resolution is limited. ΔΣ-DCOs can achieve a high resolution at the cost of high power consumption. A multi-stage capacitance shrinking technique was proposed in this paper to address the tradeoff mentioned above. The unit variable capacitance of the LC tank was largely reduced by the bridging capacitors and the number of stages. A current-reuse technique was used to further lower the power. Based on the above techniques, the prototype was fabricated using a 130-nm complementary MOS (CMOS) technology with multiple supplies (0.5~0.7 V for the DCO core, 1.2 V for the buffer). The measurement results showed that the phase noise at a 0.6-V supply was −126.27 dBc/Hz at 1 MHz and −125.9480 dBc/Hz at 1 MHz at the carriers of 2.4 GHz and 2.5 GHz, respectively. The best figure of merit (FoM) of 195.68 was obtained when VDD = 0.6 V. The DCO core consumed 1.1 mA at a 0.6-V supply.

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An Ultra-Low Power 1.7-2.7 GHz Fractional-N Sub-Sampling Digital Frequency Synthesizer and Modulator for IoT Applications in 40 nm CMOS

Cited by 54 publications

References 15 publications

A 0.5-V 1.6-mW 2.4-GHz Fractional-N All-Digital PLL for Bluetooth LE With PVT-Insensitive TDC Using Switched-Capacitor Doubler in 28-nm CMOS

A 0.5-V 1.6-mW 2.4-GHz Fractional-N All-Digital PLL for Bluetooth LE With PVT-Insensitive TDC Using Switched-Capacitor Doubler in 28-nm CMOS

A comprehensive in-depth study of tri-state inverter based DCO

A 0.5~0.7 V LC Digitally Controlled Oscillator Based on a Multi-Stage Capacitance Shrinking Technique

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