An ultra low-power, high-PSRR CMOS voltage reference

Abstract

Fig 1. Conventional voltage reference circuits based on difference between V GS voltages of (a) an nMOS and a pMOS transistor, and (b) two nMOS transistors Abstract-A CMOS voltage reference based on the difference between the gate-source voltages of pMOS and nMOS transistors operating in subthreshold region is presented. Power consumption is optimized by subthreshold design and minimizing the number of passive elements in any circuit branches from supply to the ground. A reference voltage of 912 mV with a temperature coefficient of 68 ppm/°C from −40 °C to 120 °C is achieved. Proposed voltage reference circuit can operate at supply voltages ranging from 1.5 V to 3.5 V while the current drawn from supply is at most 47 nA. Power supply rejection ratio without any filtering capacitor at 100 Hz and 10 MHz frequencies are about −68 dB and −70 dB respectively.