An Ultralow-Power Mixed-Signal Back End for Passive Sensor UHF RFID Transponders

Abstract

This paper describes the design of mixed-signal back end for an ultrahigh-frequency sensor-enabled radio-frequency identification transponder in full compliance with the Electronic Product Code Class-1 Generation-2 protocol, defined in the standard ISO 18000-6C. The chip, implemented in a low-cost 0.35-µm CMOS technology process, includes a baseband processor, an analog-to-digital converter (ADC) to digitize the signal acquired from the external sensor, and some auxiliary circuitry for voltage regulation and reference generation. The proposed solution uses two different supply voltages, one for the processor and the other for the mixed-signal circuitry, and defines a novel communication protocol between both blocks so that analog readouts are minimally affected by the digital activity of the tag. The whole system was first functionally validated by exhaustively testing with external dc power supplies ten prototype samples, and then, the two main blocks, processor, and ADC were individually tested to assess their performance limits. Regarding the baseband processor, experiments were performed toward the calculation of its packet error rate (PER) under two typical biasing configurations of passive tags, using either crude clamps or regulators. It was found that the regulated biasing outperforms the clamping solution and obtains a PER of 3 × 10 −3 with a supply voltage of 0.75 V. The current consumption of the processor during the reception and response to a Read command at maximum backward rate is only 2.2 µA from a 0.9-V supply. Regarding the ADC, it is a 10-b successive approximation register converter which obtains 9.41 b of effective resolution at 2-kS/s sampling frequency with a power consumption of 250 nW, including the dissipation of a current generation cell and the clock generation circuitry, from 1-V supply.

A Partitioning Approach to RFID Identification

“…For the reader, it does not need to change the original hardware circuit. For a tag, the added extra counter is negligible relative to the overall circuit scale of modern tags [40]. Thus, these modifications are based on the scope of changes allowed by existing EPC C1 Gen2 standard and hardware circuit and…”

Behavioral Simulation of ISO 18000-6 Type-C Class 1 Gen2 Protocol for RFID UHF Transponder and its Application as Anti-collision Protocol in Interference Case

“…Generally, the number of states of the FSM and the other included features determine the complexity and functionality of the whole tag [3], [19], [20]. The architecture has eight major sub modules classified into three principal sections [21], [22]: The command detection module is in charge of receiving, decoding and validating the command transmitted by the interrogator.…”

Design and Implementation of a RF Powering Circuit for RFID Tags or Other Batteryless Embedded Devices

“…The applications of RFID technologies, including supply chain management, access control to buildings, public transportation, airport baggage handling, express parcel delivery and logistics, have increased rapidly in recent years [ 1 – 3 ]. Owing to its wireless and far field measurement capabilities, the combination of RFID technology and wireless sensing networks has also found a large number of applications such as environmental monitoring and healthcare devices [ 4 – 6 ]. RFID tags are often classified as passive or active.…”