Anaconda: simulation-based synthesis of analog circuits via stochastic pattern search

Phelps, R.; Krasnicki, M.; Rutenbar, R.A.; Carley, L.R.; Hellums, J.R.

doi:10.1109/43.848091

Cited by 262 publications

(94 citation statements)

References 42 publications

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“…transistor sizes) for a given analog circuit by iteratively running circuit simulations with new design candidates [1][2][3]. One challenge that most simulation-based circuit optimizers face is the long execution time, due to a large number of simulation runs typically required to find the optimal design.…”

Section: Introductionmentioning

confidence: 99%

Investigations on the Optimal Support Vector Machine Classifiers for Predicting Design Feasibility in Analog Circuit Optimization

Lee

Kim

2015

JSTS:Journal of Semiconductor Technology and Science

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Abstract-In simulation-based circuit optimization, many simulation runs may be wasted while evaluating infeasible designs, i.e. the designs that do not meet the constraints. To avoid such a waste, this paper investigates the use of support vector machine (SVM) classifiers in predicting the design's feasibility prior to simulation and the optimal selection of the SVM parameters, namely, the Gaussian kernel shape parameter γ and the misclassification penalty parameter C. These parameters affect the complexity as well as the accuracy of the model that SVM represents. For instance, the higher γ is good for detailed modeling and the higher C is good for rejecting noise in the training set. However, our empirical study shows that a low γ value is preferable due to the high spatial correlation among the circuit design candidates while C has negligible impacts due to the smooth and clean constraint boundaries of most circuit designs. The experimental results with an LC-tank oscillator example show that an optimal selection of these parameters can improve the prediction accuracy from 80 to 98% and model complexity by 10×.

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Section: Introductionmentioning

confidence: 99%

Investigations on the Optimal Support Vector Machine Classifiers for Predicting Design Feasibility in Analog Circuit Optimization

Lee

Kim

2015

JSTS:Journal of Semiconductor Technology and Science

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“…Analog design problem is typically an over constrained problem with many degrees of freedom and many performance requirements and it is still characterized by the lack of a unique and structured design flow definition. The majority of the applied techniques and tools used to solve the analog problem, such as DELIGHT.SPICE [1], ANACONDA [2], AMGIE [3], and APE [4], among many others [5], are based on powerful numerical optimization engines (e.g. evolutionary algorithms, geometric programming,) conjugated with evaluation engines (e.g.…”

Section: Introductionmentioning

confidence: 99%

Analog circuits optimization based on evolutionary computation techniques

2010

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1 -This paper presents a new design automation tool based on a modified genetic algorithm kernel, in order to increase efficiency on the analog circuit and system design cycle. It combines a robust optimization with corners, machine learning modeling and distributed processing capability able to deal with multi-objective and highly constrained optimization problems. The resulting optimization tool, simulation capabilities, and extensible architecture are presented and the improvement in design productivity is demonstrated for the design of robust CMOS operational amplifiers.

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“…Further, the resulting designs are not easy to be ported to a finer technology. Attempts to synthesize analog circuits have had limited success [6][7][8][9][10][11][12][13][14][15]. Hence, it is desired to improve the design automation support for analog/mixed-signal blocks.…”

Section: Design Automation and Analog Designmentioning

confidence: 99%

Design of VCO-based ADCs

Unnikrishnan¹

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Today's complex electronic systems with billions of transistors on a single die are enabled by the aggressive scaling down of the device feature size at an exponential rate as predicted by the Moore's law. Digital circuits benefit from technology scaling to become faster, more energy efficient as well as more area efficient as the feature size is scaled down. Moreover, digital design also benefits from mature CAD tools that simplify the design and cross-technology porting of complex systems, leveraging on a cell-based design methodology. On the other hand, the design of analog circuits is getting increasingly difficult as the feature size scales down into the deep nanometer regime due to a variety of reasons like shrinking voltage headroom, reducing intrinsic gain of the devices, increasing noise coupling between circuit nodes due to shorter distances etc. Furthermore, analog circuits are still largely designed with a full custom design flow that makes their design and porting tedious, slow, and expensive. In this context, it is attractive to consider realizing analog/mixed-signal circuits using standard digital components. This leads to scaling-friendly mixed-signal blocks that can be designed and ported using the existing CAD framework available for digital design. The concept is already being applied to mixed-signal components like frequency synthesizers where all-digital architectures are synthesized using standard cells as basic components. This can be extended to other mixed-signal blocks like digital-to-analog and analogto-digital converters as well, where the latter is of particular interest in this thesis.A voltage-controlled oscillator (VCO)-based analog-to-digital converter (ADC) is an attractive architecture to achieve all-digital analog-todigital conversion due to favorable properties like shaping of the quantization error, inherent anti-alias filtering etc. Here a VCO operates as a signal integrator as well as a quantizer. A converter employing a ring oscillator as the VCO lends itself to an all-digital implementation.iii In this dissertation, we explore the design of VCO-based ADCs synthesized using digital standard cells with the long-term goal of achieving high performance data converters built from low accuracy switch components. In a first step, an ADC is designed using vendor supplied standard cells and fabricated in a 65 nm CMOS process. The converter delivers an 8-bit ENOB over a 25 MHz bandwidth while consuming 3.3 mW of power resulting in an energy efficiency of 235 fJ/step (Walden FoM). Then we utilize standard digital CAD tools to synthesize converter designs that are fully described using a hardware description language. A polynomial-based digital post-processing scheme is proposed to correct for the VCO nonlinearity. In addition, pulse modulation schemes like delta modulation and asynchronous sigma-delta modulation are used as a signal pre-coding scheme, in an attempt to reduce the impact of VCO nonlinearity on converter performance. In order to investigate the scaling benefit...

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Anaconda: simulation-based synthesis of analog circuits via stochastic pattern search

Cited by 262 publications

References 42 publications

Investigations on the Optimal Support Vector Machine Classifiers for Predicting Design Feasibility in Analog Circuit Optimization

Investigations on the Optimal Support Vector Machine Classifiers for Predicting Design Feasibility in Analog Circuit Optimization

Analog circuits optimization based on evolutionary computation techniques

Design of VCO-based ADCs

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