Analog and Digital Circuit Design in 65 nm CMOS: End of the Road?

Abstract

This special session adresses the problems that designers face when implementing analog and digital circuits in nanometer technologies. An introductory embedded tutorial will give an overview of the design problems at hand : the leakage power and process variability and their implications for digital circuits and memories, and the reducing supply voltages, the design productivity and signal integrity problems for embedded analog block s. Next, a panel of experts from both industrial semiconductor houses and design companies, EDA vendors and research institutes will present and discuss with the audience their opinions on whether the design road ends at marker "65nm" or not.

Globally Reliable Variation-Aware Sizing of Analog Integrated Circuits via Response Surfaces and Structural Homotopy

“…3 and 4 2 show two iterations of MBO on a simple 1-D problem. Here, model uncertainty is merely the distance to the closest training point 3 :…”

“…As of 2006, 70% of systems on chips or systems in packages have some analog functionality, up from 50% in 2005 and 10% in 1999 [2]. We need a means to design analog circuits which meet performance goals, have high yield, with low area, all designed fast enough to succeed in tight time-to-market schedules [3].…”

Optimal sizing of configurable devices to reduce variability in integrated circuits

“…As technologies become smaller, leakage becomes a greater problem in analogue circuits, indeed this is one of the most significant problems for digital design [4]. Variability in process parameters is a far greater problem in DSM nodes especially as device models are reaching their limits of predictability [5]. To overcome these significant issues, fundamentally new design techniques are required.…”

Architecture for Isolating Defective Two Port SRAM Memories

“…Due to this scaling, process variations increase significantly causing parametric variations in transistor feature sizes and threshold voltages due to random dopant fluctuations, line edge roughness, sub-wavelength lithography [1] [2]. The threshold voltage mismatch between the neighboring transistors in a cell, results in the failure of a cell.…”