Analog-DFE-based 16Gb/s SerDes in 40nm CMOS that operates across 34dB loss channels at Nyquist with a baud rate CDR and 1.2V&lt;inf&gt;pp&lt;/inf&gt; voltage-mode driver

Joy, A.K.; Mair, Hugh; Lee, Hae-Chang; Feldman, Arnold; Portmann, C.; Bulman, Neil; Crespo, Eugenia Cordero; Hearne, Peter; Huang, Peng; Kerr, Ben; Khandelwal, Pulkit; Kuhlmann, Franz; Lytollis, S.; Machado, Joaquim; Morrison, Casey; Morrison, Scott; Rabii, Shahriar; Rajapaksha, Dushmantha; Ravinuthula, Vishnu; Surace, Giuseppe

doi:10.1109/isscc.2011.5746349

“…For these reasons, a variable delay of up to 20ps is included in each of the four CML-to-CMOS converters in order to compensate for clock skew. [5,6]. The maximum vertical eye opening occurs when the main cursor, h 0 , is at time T-this is our desired sampling phase.…”

mentioning

confidence: 99%

A blind baud-rate ADC-based CDR

Chen¹,

Liang²,

Sheikholeslami³

et al. 2013

2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers

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ADC-based receivers process the received data in the digital domain, eliminating the need for much of the analog front end. In addition, a feed-forward blind architecture [1,2] eliminates the feedback loop between digital and analog domains so that the ADC and digital CDR can be designed and simulated independently. Previous works [1,2] sampled the incoming data at 2 samples per UI and at 1.45 samples per UI to achieve 5Gb/s and 6.875Gb/s, respectively. To further increase the data rate to 10Gb/s, we sample at baud rate (1 sample per UI). Existing baud-rate architectures [3] rely on a phase-tracking clock to sample at the middle of the data eye. This paper presents a blind baud-rate CDR, fabricated in 65nm CMOS. At 10Gb/s, the CDR demonstrates a high-frequency jitter tolerance of 0.19UI with ±300ppm of frequency offset. Also, the CDR demonstrates successful operation with 1000ppm offset, which amounts to sub-baud-rate sampling. Figure 7.4.1 illustrates the main challenge in the blind baud-rate sampling approach. Given an ideal channel, the data eye is open when sampled with a phase range spanning 1UI. However, with blind sampling, frequency offset between the data and receiver clock will cause the baud-rate sampling phase to shift continuously across a 1UI window. When the sampling occurs near the boundary, any high-frequency jitter may shift the sampling outside the 1UI phase range, resulting in the loss of data bits (i.e., zero jitter tolerance). To increase jitter tolerance, we introduce a controlled amount of ISI in the data by using a rectangular filter implemented as an integrate-and-dump (I&D) circuit [4] in the receiver front end. A 1UI rectangular filter, convolved with the ideal channel, spreads the pulse response to 2UI. If we have a perfect DFE to cancel all postcursor ISI, then the eye would be open for a range of 1.5UI. If the blind samples shift beyond the 1UI window, there is still a remaining jitter margin of 0.5UI pp . A 2UI rectangular filter increases this margin to 1UIpp and results in a symmetric eye opening with respect to the blind sampling window. For these reasons, we choose a 2UI I&D circuit in our design. The front end consists of four interleaved I&D and ADC blocks, each operating at 2.5GS/s. The I&D circuit integrates over 1UI intervals and samples the result, which the ADC converts into 5b digital values that are demuxed into 16 parallel samples. The digital CDR adds adjacent 5b 1UI I&D samples to synthesize 6b 2UI I&D samples. Since our ADC resolution is limited to 5 bits, if we were to obtain 2UI I&D samples directly in the analog domain and feed them to the ADC, we would have lost the added resolution.The digital CDR contains a feedback loop including a data interpolator, a speculative 2-tap DFE, a speculative Mueller-Muller phase detector (MMPD), and a conventional 2 nd -order loop filter. The data interpolator estimates the desired sample at the average interpolation phase (ϕ avg ) by linearly combining neighbouring blind samples. Given a negative frequency offset (i.e., data ...

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“…Here, both techniques utilize segmentation of the output driver to implement the different output voltage levels for equalization. In the design in [2] and [4], a 1 − α percentage of the output segments is controlled by the main-cursor tap, and an α percentage is controlled by the postcursor tap, with the output segments sized to ensure that all parallel combinations maintain proper source termination. Note that, as shown in Table I, the current drawn from the output driver supply V REF varies with the output level, with all current flowing out into the channel during the maximum output swing and a portion being sunk at the transmitter during the deemphasized level.…”

Section: Transmitter Equalization Techniquesmentioning

confidence: 99%

“…1(d) shows a simplified schematic of the hybrid driver proposed in this brief which combines the low output current levels of a voltage-mode driver to implement the main tap and a parallel current-mode driver to implement the postcursor tap with minimal predriver complexity. While parallel current drivers have previously been implemented with voltagemode drivers as swing enhancers [4], this implementation improves driver energy efficiency by eliminating the voltagemode-driver segmentation, as the equalization coefficient is set via the current-mode-driver tail-current DAC setting.…”

Section: Transmitter Equalization Techniquesmentioning

confidence: 99%

“…How- ever, the potential power savings of voltage-mode drivers generally degrade with the introduction of transmit equalization and overheads associated with maintaining proper source termination. In order to generate the different output voltage levels for transmit equalization, significant output-stage segmentation is required in voltage-mode drivers which implement resistor divider [2]- [4] and channel shunting approaches [5]. This segmentation increases predriver complexity, resulting in degraded dynamic-power consumption.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A 6-Gbit/s Hybrid Voltage-Mode Transmitter With Current-Mode Equalization in 90-nm CMOS

Song

¹

,

Palermo

²

2012

IEEE Trans. Circuits Syst. II

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Abstract-Low-power (LP) high-speed serial I/O transmitters which include equalization to compensate for channel frequency-dependent loss are required to meet the aggressive link energy-efficiency targets of future systems. This brief presents an LP serial-link-transmitter design that utilizes an output stage which combines a voltage-mode driver, which offers low staticpower dissipation, and current-mode equalization, which offers low complexity and dynamic-power dissipation. The utilization of current-mode equalization decouples the equalization settings and termination impedance, allowing for a significant reduction in predriver complexity relative to segmented voltage-mode drivers. Proper transmitter series termination is set with an impedance control loop which adjusts the on-resistance of the output transistors in the driver voltage-mode portion. Further reductions in dynamic-power dissipation are achieved through scaling the serializer and local clock distribution supply with data rate. Fabricated in a 1.2-V 90-nm LP CMOS process, the transmitter supports an output swing range of 100-400 mV ppd and up to 6 dB of equalization and includes output-duty-cycle control. The transmitter achieves 6-Gbit/s operation at 1.26-pJ/bit energy efficiency with 300-mV ppd output swing and 3.72-dB equalization.Index Terms-Channel impedance matching, high-speed link, I/O, low power (LP), transmit equalization.

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“…For these reasons, a variable delay of up to 20ps is included in each of the four CML-to-CMOS converters in order to compensate for clock skew. Figure 7.4.4 shows the details of the speculative MMPD [5,6]. The maximum vertical eye opening occurs when the main cursor, h 0 , is at time T-this is our desired sampling phase.…”

mentioning

confidence: 99%

A Blind Baud-Rate ADC-Based CDR

Chen

¹

,

Liang

²

,

Sheikholeslami

³

et al. 2013

IEEE J. Solid-State Circuits

View full text Add to dashboard Cite

ADC-based receivers process the received data in the digital domain, eliminating the need for much of the analog front end. In addition, a feed-forward blind architecture [1,2] eliminates the feedback loop between digital and analog domains so that the ADC and digital CDR can be designed and simulated independently. Previous works [1,2] sampled the incoming data at 2 samples per UI and at 1.45 samples per UI to achieve 5Gb/s and 6.875Gb/s, respectively. To further increase the data rate to 10Gb/s, we sample at baud rate (1 sample per UI). Existing baud-rate architectures [3] rely on a phase-tracking clock to sample at the middle of the data eye. This paper presents a blind baud-rate CDR, fabricated in 65nm CMOS. At 10Gb/s, the CDR demonstrates a high-frequency jitter tolerance of 0.19UI with ±300ppm of frequency offset. Also, the CDR demonstrates successful operation with 1000ppm offset, which amounts to sub-baud-rate sampling. Figure 7.4.1 illustrates the main challenge in the blind baud-rate sampling approach. Given an ideal channel, the data eye is open when sampled with a phase range spanning 1UI. However, with blind sampling, frequency offset between the data and receiver clock will cause the baud-rate sampling phase to shift continuously across a 1UI window. When the sampling occurs near the boundary, any high-frequency jitter may shift the sampling outside the 1UI phase range, resulting in the loss of data bits (i.e., zero jitter tolerance). To increase jitter tolerance, we introduce a controlled amount of ISI in the data by using a rectangular filter implemented as an integrate-and-dump (I&D) circuit [4] in the receiver front end. A 1UI rectangular filter, convolved with the ideal channel, spreads the pulse response to 2UI. If we have a perfect DFE to cancel all postcursor ISI, then the eye would be open for a range of 1.5UI. If the blind samples shift beyond the 1UI window, there is still a remaining jitter margin of 0.5UI pp . A 2UI rectangular filter increases this margin to 1UIpp and results in a symmetric eye opening with respect to the blind sampling window. For these reasons, we choose a 2UI I&D circuit in our design. The front end consists of four interleaved I&D and ADC blocks, each operating at 2.5GS/s. The I&D circuit integrates over 1UI intervals and samples the result, which the ADC converts into 5b digital values that are demuxed into 16 parallel samples. The digital CDR adds adjacent 5b 1UI I&D samples to synthesize 6b 2UI I&D samples. Since our ADC resolution is limited to 5 bits, if we were to obtain 2UI I&D samples directly in the analog domain and feed them to the ADC, we would have lost the added resolution.The digital CDR contains a feedback loop including a data interpolator, a speculative 2-tap DFE, a speculative Mueller-Muller phase detector (MMPD), and a conventional 2 nd -order loop filter. The data interpolator estimates the desired sample at the average interpolation phase (ϕ avg ) by linearly combining neighbouring blind samples. Given a negative frequency offset (i.e., data ...

show abstract

Analog-DFE-based 16Gb/s SerDes in 40nm CMOS that operates across 34dB loss channels at Nyquist with a baud rate CDR and 1.2V<inf>pp</inf> voltage-mode driver

Cited by 24 publications

References 4 publications

A blind baud-rate ADC-based CDR

A blind baud-rate ADC-based CDR

A 6-Gbit/s Hybrid Voltage-Mode Transmitter With Current-Mode Equalization in 90-nm CMOS

A Blind Baud-Rate ADC-Based CDR

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