Analog I/Q FIR Filter in 55-nm SiGe BiCMOS for 16-QAM Optical Communications at 112 Gb/s

Verplaetse, Michiel; Lambrecht, Joris; Vanhoecke, Michael; Breyne, Laurens; Ramon, Hannes; Demeester, Piet; Torfs, Guy

doi:10.1109/jssc.2020.2987732

Cited by 23 publications

(5 citation statements)

References 25 publications

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“…Some skew is added between the signals to align the edges of the LSB bitstream with the MSB bitstream. In our experiment, this skew was tuned using the AWG, however, delay cells could be added to the driver input to align the edges [16]. In a transceiver, additional control loops will be required to tune both the gain and delay of the MSB.…”

Section: Resultsmentioning

confidence: 99%

50 GBd PAM4 transmitter with a 55nm SiGe BiCMOS driver and silicon photonic segmented MZM

Breyne¹,

Ramon²,

Gasse³

et al. 2020

Opt. Express

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We demonstrate an optical transmitter consisting of a limiting SiGe BiCMOS driver co-designed and co-packaged with a silicon photonic segmented traveling-wave Mach-Zehnder modulator (MZM). The MZM is split into two traveling-wave segments to increase the bandwidth and to allow a 2-bit DAC functionality. Two limiting driver channels are used to drive these segments, allowing both NRZ and PAM4 signal generation in the optical domain. The voltage swing as well as the peaking of the driver output are tunable, hence the PAM4 signal levels can be tuned and possible bandwidth limitations of the MZM segments can be partially alleviated. Generation of 50 Gbaud and 53 Gbaud PAM4 yields a TDECQ of 2.8 and 3.8 dB with a power efficiency of 3.9 and 3.6 pJ/bit, respectively; this is the best reported efficiency for co-packaged silicon transmitters for short-reach datacenter interconnects at these data rates. With this work, we show the potential of limiting drivers and segmented traveling-wave modulators in 400G capable short-reach optical interconnects.

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Section: Resultsmentioning

confidence: 99%

50 GBd PAM4 transmitter with a 55nm SiGe BiCMOS driver and silicon photonic segmented MZM

Breyne¹,

Ramon²,

Gasse³

et al. 2020

Opt. Express

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“…Transmission line segments are used to create the delay between the different gain segments of the FIR filter. Active delay solutions as demonstrated in [15] are power consuming. To overcome this, we proposed a mixedsignal FIR filter which we implemented in a full PAM-4 multiplexer [16].…”

Section: Pam-4 Multiplexer With 7-tap Ffementioning

confidence: 99%

High-Speed SiGe BiCMOS Circuits for Optical Communication

Torfs,

Moeneclaey,

Lambrecht

et al. 2023

2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)

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This paper presents an overview of SiGe BiCMOS circuits for next-generation optical communication links targeting 100 GBd PAM4 modulation per wavelength to support 4-lane 800Gb and 8-lane 1.6Tb Ethernet. Signal generation at these rates is challenging. For this, an analog multiplexer making use of return-to-zero (RZ) modulation is presented. The explicit RZ generation enables equalization of the interleaved signal. Higher equalization orders are obtained with a 120 GBd PAM4 4-to-1 multiplexer with a mixed-signal 7-tap feedforward equalizer. The equalizer consists of a combination of digital delay cells and analog delay cells enabling a compact and power efficient solution. Quadchannel modulator drivers and receivers finish the required highspeed circuits. Based on traveling-wave architectures high gainbandwidth products are realized.

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“…The optical signals are coupled to the ICR through 8(f). Single stage analog domain equalizers [1,6] or their cascade combination [18] can be used for the equalization.…”

Section: Proof-of-concept Demonstrationmentioning

confidence: 99%

“…The enhanced energy efficiency and reduced complexity in the ASP approach are attributed to the omission of analog to digital converters (ADCs) and massive number of operations in digital signal processors (DSPs). In the literature, all-analog coherent receiver solutions compensating for dispersion and laser offsets are presented in [1,3,[5][6][7]. When projected to the 400ZR standard, the ASP approach implemented in a 7 nm FinFET technology can save ∼3.6 W compared to its digital counterpart [5].…”

Section: Introductionmentioning

confidence: 99%

An Analog Signal Processing EIC-PIC Solution for Coherent Data Center Interconnects

Chugh¹,

Ashok²,

Jain³

et al. 2022

Preprint

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Data center interconnects (DCIs) will have to support throughputs of 400 Gbps or more per wavelength in the near future. To achieve such high data rates, coherent modulation and detection is used, which conventionally requires high-speed data conversion and signal processing in the digital domain. Alternatively, high-speed signal conditioning and processing could be carried out in co-designed photonic and electronic integrated circuits, in the optical and electrical analog domains, respectively, to achieve reduced power consumption, latency, form factor, and cost. A few demonstrations of analog domain processing electronic integrated circuits (EICs), including those of equalizer and carrier phase recovery (CPR) modules showcase progress in this direction in the literature. In this brief, for the first time, we present integration of a silicon photonic integrated coherent receiver (ICR) module with a CPR module, as a part of a complete coherent receiver solution. A phase shifter in the ICR (fabricated in a 220 nm silicon-on-insulator technology) receives feedback from a CPR EIC, and the combination compensates for the time varying phase offset between the modulated signal and the unmodulated carrier in the closed loop configuration. In this proof-of-concept demonstration, we present experimental results obtained from the stand-alone silicon photonic ICR along with its system level integration with CPR chip, for QPSK signals. The technique can be extended to a higher-order modulation format, such as 16-QAM, for data rate scaling. The proposed scheme is suitable for homodyne systems, such as polarization multiplexed carrier based self-homodyne links.

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Analog I/Q FIR Filter in 55-nm SiGe BiCMOS for 16-QAM Optical Communications at 112 Gb/s

Cited by 23 publications

References 25 publications

50 GBd PAM4 transmitter with a 55nm SiGe BiCMOS driver and silicon photonic segmented MZM

50 GBd PAM4 transmitter with a 55nm SiGe BiCMOS driver and silicon photonic segmented MZM

High-Speed SiGe BiCMOS Circuits for Optical Communication

An Analog Signal Processing EIC-PIC Solution for Coherent Data Center Interconnects

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