Analog performance of Si junctionless tunnel field effect transistor and its improvisation using III–V semiconductor

Experimental demonstration of improved analog device performance of nanowire-TFETs

“…The achieved maximum gain is significantly smaller than for some TFET simulations with excellent output saturation [6]. However, A i is comparable to simulations where an unconventional conductance behavior for higher values of V g is taken into account [7]. In comparison to experimental analog TFET-data by Der Agopian et al [10] the presented TFETs show significantly higher I on and g m while holding a comparable A i at smaller V d and V gt .…”

“…This increase could be attributed to a drain induced lowering of the drain-Schottky-barrier [17] and is more pronounced for the 10 nm wires due to the lower source tunnel resistance. However, in analogy to simulations by Goswami et al [7] the conductance behaves unconventionally for higher gate voltage and exhibits a maximum that shifts to higher drain-voltages with increasing V gt . We observed similar behavior in the planar TFETs as shown in Fig.…”

“…Up to now, experimental as well as theoretical works focused mainly on digital applications of TFETs. Only a few theoretical studies on analog and sensor application of TFETs have been published [3][4][5][6][7][8][9] and even less experimental data are available [10,11]. The transconductance g m = oI d /oV g , output conductance g d = oI d /oV d and intrinsic voltage gain A i = g m /g d are important figures of merit for analog circuit design.…”

Representation of heterostructure electrically doped nanoscale tunnel FET with Gaussian-doping profile for high-performance low-power applications

“…It has provided N + -I-P + for N-JLTFETs similar to doping profile of an N-TFET using two methods. One method is the use of the charge plasma concept, wherein the desired doping profile is created by choosing appropriate workfunctions for the gates called the polarity gate (PG) located at the source region and the control gate (CG) located at the middle with a lower workfunction than PG for being a nearly intrinsic channel [24][25][26][27]. As the same way, p-channel JLTFET has the similar structure [28].…”

A JL-SDR-IMPATT Device with Improved Efficiency

“…We have chosen the metal work function as 4.27 eV and 5.93eV for the CG and PG electrode, to make the layer beneath the CG and the PG electrode n-type and p+-type respectively [18][19]. As soon as the contact is made between metal oxide and the N+ semiconductor, the electrons will flow from the semiconductor to the metal and thus Fermi level goes down and in equilibrium this level is aligned with the Fermi level of the metal.…”