Analog/RF circuit design techniques for nanometerscale IC technologies

Abstract

Abstract:CMOS evolution introduces several problems in analog design. Gate-leakage mismatch exceeds conventional matching tolerances requiring active cancellation techniques or alternative architectures. One strategy to deal with the use of lower supply voltages is to operate critical parts at higher supply voltages, by exploiting combinations of thin-and thick-oxide transistors. Alternatively low voltage circuit techniques are successfully developed. In order to benefit from nanometer scale CMOS technology, more functionality is shifted to the digital domain, including parts of the RF circuits. At the same time, analog control for digital and digital control for analog emerges to deal with current and upcoming imperfections.

A design example of a 65 nm CMOS operational amplifier

“…The gate leakage increases the mismatch [3]. The conventional way to reduce mismatch is to spend more gate area [4,5].…”

“…For digital circuits as for instance inverters, the minimum gain according to [3] is about 10 (20 dB). The low supply voltages and the finite sub-threshold swing lead to a static power consumption of digital CMOS circuits.…”

“…However, if the speed of the circuit has to be constant, then the wider transistors need more power, because the additional capacitance has to be charged/discharged [6]. According to [3], the following formula can be used for estimation of mismatch under consideration of gate leakage:…”

Linearity and Analog Performance Analysis of Double Gate Tunnel FET: Effect of Temperature and Gate Stack

“…The continuous scaling of CMOS technology has resulted in high speed MOS devices suitable for analog RF applications [1]. The modern day communication requires low distortion and linear systems as a building block for their design.…”

Inverter-based 1 V analog front-end amplifiers in 90 nm CMOS for medical ultrasound imaging

“…Using such scaled down deep submicron CMOS technologies after analog-to-digital (ADC) conversion in the signal processing chain will greatly improve the overall ultrasound system performance in terms of area and power. From the integration aspects, it is better to also design the front-end analog amplifiers in deep submicron technologies, although this imposes many challenges in the design of analog integrated circuits in scaled down deep submicron CMOS technologies because of low supply voltages [13][14][15][16][17].…”