Analog-to-digital conversion using noise shaping and time encoding

Abstract

Low-voltage CMOS technologies pose new problems in the design of multibit continuous-time sigma-delta modulators. One of these problems is the implementation of the coarse quantizer with an array of voltage comparators. This work presents a novel architecture of multibit continuous-time sigma-delta modulator that employs a time encoding quantizer and irregular sampling instead of a flash analog-to-digital converter. The time-encoding quantizer is based in a modulated oscillator that produces a two-level signal. A digital decoder converts the binary signal into an irregularly sampled multibit signal that is interpolated and fed back into the loop filter of the sigma-delta modulator. This architecture is especially adequate for low-voltage technologies due to the absence of a resistive reference ladder in the quantizer and may permit a significant reduction of the complexity of the existing continuous-time sigma-delta modulators.

Time-to-digital converters based on event-driven successive charge redistribution: A theoretical approach

“…Time encoding of signal values consists simply in converting amplitude information of an analog signal into time information [2][3][4][5][6][7][8][9][10][11]. A discrete sample of the analog signal is then represented by a time-difference variable as the quantity of time between two events.…”

“…The conventional sampling is replaced with asynchronous mapping of analog signal value into the time domain. Existing implementations use a level-crossing sampling [14][15][16][17][18], asynchronous Sigma-Delta modulator [6,7], or a hybrid approach [8,19]. The A-ADCs based on the levelcrossing sampling [20,21] are the instantaneous value converters, while the A-ADCs with TEMs serve as the mean value converters due to inherent integration properties [6].…”

“…Most approaches to asynchronous analog-to-digital conversion based on time encoding use the clock-based TDCs where the time discretization is based on counting periods of a high frequency (local) reference clock during the discretized time intervals, e.g. [2,[5][6][7][8][9]14,23]. Existence of clock-based TDC in the AADCs proves that the process of removing the clock from the A-ADCs has not yet become a normal practice.…”

High Speed On-Chip Signal Generation for Debug and Diagnosis

“…Traditionally, information has been processed and encoded in the voltage/amplitude domain; however, more recently the encoding of information in time has gained considerable popularity [23] and [6]. Time mode signal processing involves encoding the information in the form of time difference variables using phase modulation.…”

A 0.08 mm², 7mW Time-Encoding Oversampling Converter with 10 bits and 20MHz BW in 65nm CMOS

“…These new ΣΔ ADC architectures can neatly compete in FoM and area with the latest SAR and pipeline converters [3], [4] and clearly surpass them in linearity, configurability and anti aliasing features. The converter architecture presented in this paper has been disclosed from the theoretical point of view in [5] and belongs to this new class of oversampled converters. The proposed ADC consists of a CT-ΣΔ modulator whose quantizer is implemented as a PWM modulator.…”