A 0.08 mm², 7mW Time-Encoding Oversampling Converter with 10 bits and 20MHz BW in 65nm CMOS

Abstract

This work presents an area-and power-efficient realization of a new Time-Encoding Oversampling Converter (TEOC) consisting of a 3rd-order CT loop filter and a selfoscillating PWM which displays similar performance than a standard multibit CT-ΣΔ modulator but has the complexity of a single bit design. The introduced Time-Encoding Quantizer (TEQ) is implemented inside a ΣΔ modulator by replacing a multibit quantizer. An innovative TEQ is used to overcome design issues in a 1.0V supply-voltage 65nm digital CMOS technology. The TEQ allows an exchange of amplituderesolution by time-resolution. The approach of time-resolution alleviates the scaling difficulties of mixed-signal circuits in nano-scale technologies. The TEOC features a 63dB dynamicrange and a peak-SNDR of 61dB over a 20MHz signal bandwidth. Clocked at 2.5GHz, the complete ADC consumes 7mW from a single 1.0V supply, including also the reference buffers. The ADC core results in an attractively small area of 0.08mm² and in a Figure-of-Merit (FoM=Pwr/2⋅BW⋅2 ENOB ) of 0.17pJ/conversion-step.

Delta-Sigma A/D-Converters

“…This A/D-converter was presented at ESSCIRC 2010 conference [8] and published in IEEE Journal of Solid-State Circuits [7]. This A/D-converter was presented at ESSCIRC 2010 conference [8] and published in IEEE Journal of Solid-State Circuits [7].…”

“…5.25. 8 Due to the rising behavior of the STF, the SNR-curve shows a peaking 2 dB below full-scale, since the delta-sigma modulator is close to its overload condition for tones at higher input frequencies. The feedback signals is damped at higher frequencies leading to less Measured signal-to-noise and distortion ratio feedback causing an increased signal amplitude.…”

“…2. This A/Dconverter was presented at ESSCIRC 2010 conference [8] and published in IEEE Journal of Solid-State Circuits [7]. Second, the CT feedback circuitry leads to a less stable loop due to the Excess Loop Delay (ELD).…”

VCO-based sigma delta modulator with PWM precoding

“…One of these topologies is based on a voltage controlled oscillator (VCO) [1], which provides a multibit quantised output with a simple ring oscillator but at the expense of uncompensated distortion due to the nonlinear voltage-to-frequency conversion of the VCO. On the other hand, pulse width modulation (PWM) has been used to implement efficient ADCs but still requiring either linear integrators [2] or a power consuming time to digital converter (TDC) [3]. In this Letter, we present an architecture that combines both the VCO and the PWM approaches to implement a converter that mitigates the nonlinearity problems of VCOs without requiring high performance operational amplifiers.…”