Analysis and Design of a Low-Voltage, Low-Power, High-Precision, Class-AB Current-Mode Subthreshold CMOS Sample and Hold Circuit

Abstract

This paper proposes the design of a current-mode sample and hold circuit using subthreshold MOSFETs. The proposed circuit combines negative feedback and the compressive characteristic of a class-AB weak inversion transconductor to achieve low switching error, high signal-to-noise ratio and high dynamic range from a low supply voltage and very low current consumption. The paper also provides a feedback analysis of current mode sample and hold circuits. Several design issues including circuit stability, mismatch, linearity, noise, and power consumption are discussed and a comparison of class-A and class-AB versions of subthreshold sample and hold circuits is made. The design verification of the proposed class-AB current mode sample and hold circuit is done by circuit simulations using 0.13 m CMOS model parameters. The results show that, from a 0.6 V supply and with a power consumption of 27.5 nW, the proposed circuit provides 73 dB signal-to-noise ratio, 77 dB dynamic range, and a figure of merit of 1.9 nW/MHz.

Low‐power sample and hold circuits using current conveyor analogue switches

“…The input waveform is sampled at the output when switch is ON and the input voltage is held on the capacitor and appears at the output when switch is OFF. Many S/H circuits have been proposed base on different active devices such as diode bridge-based S/H circuits [4][5][6], follower circuit-based S/H circuits in [7][8][9][10], operational transconductance amplifier-based S/H circuits in [11][12][13][14][15], amplifier-based S/H circuits in [16][17][18][19][20][21][22][23], CCII-based S/H circuits in [24,25]. To obtain sampling input signal and holding input signal, there are three techniques to control state of these active devices: the first technique is supplying clocks through bias current sources [2][3][4][5][6], the second technique is supplying clocks at the input of differential pairs [7][8][9][10], and third technique is supplying clock to control switches [11][12][13][14][15][16][17][18][19][20][21][22]…”

“…To obtain sampling input signal and holding input signal, there are three techniques to control state of these active devices: the first technique is supplying clocks through bias current sources [2][3][4][5][6], the second technique is supplying clocks at the input of differential pairs [7][8][9][10], and third technique is supplying clock to control switches [11][12][13][14][15][16][17][18][19][20][21][22][23][24][25]. Typically, the switch in [11][12][13][14][15][16][17][18][19][20][21][22][23][24][25] is implemented using metal oxide semiconductor (MOS) transistors and clock signal will be applied through its gate. Although, these S/H circuits provide high-speed operation and high-resolution data conversion that suitable for modern communication systems, but some circuits suffer from the hardware complexity, high-power consumption and non-overlapped clock signal requirements.…”

“…Comparison between the proposed circuit and previous low-power S/H circuits Parameter Unit This work(Fig. 2) Chatterjee et al[13] Ferreira et al[20] Sawigun et al[23] Harb[27] …”

Methodology for designing and verifying switched‐capacitor sample and hold circuits used in data converters

“…Therefore care must be taken in the design of each of their components in order to guarantee a proper and a stable data conversion [7]. Many topologies of the S/H circuits for the ADCs have been proposed such as a bipolar circuit and a current mode circuit in [8, 9], respectively. However, the option of preference is the switched‐capacitor circuits as in [10].…”

Low‐Voltage PTAT Voltage Reference with Area Efficiency Improved

“…Since the low-power circuits mentioned above achieve low-frequency measurement, analog signal processing, and primitive communication, which are ordinary synthesized with elementary building blocks, design can focus on decreasing the power consumed by amplifiers, switches, oscillators, filters, and biasing or reference circuits. An approach to such designs is the use of MOSFETs operating in the subthreshold region [1][2][3][4][5][6][7][8][9][10] to address the design concerns of the signal-to-noise ratio of amplifiers, the on-resistance of switches, and phase noise of oscillators.…”