Analysis of Deadbeat Control for an Integer-N Charge-pump PLL

2018

Circuit Theory & Apps

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In this paper, we present a new design of phase frequency detector (PFD) without reset, such that the blind zone and dead zone issues in the phase locked loop are annihilated. The PFD is designed using transmission gate-based latches, which produce UP and DOWN pulses only when there is a distinct phase difference between the reference and divided frequencies. Thus, the continuous pulses that get produced by the conventional NAND gate-based latches are avoided, leading to reduced power consumption of the PFD. The charge pump makes use of an op-amp used as a buffer, to reduce the current mismatch. The loop filter used is of second order, and the voltage-controlled oscillator is of conventional current-starved type. The divider makes use of true single-phase clock latches. It was found that the phase locked loop with new design of PFD, compared with the conventional design, consumes 27% lesser power, and the lock time is decreased by 79%. In addition, it was found that the control voltage swing is reduced by 71%, which leads to much lesser spur content at the output of the voltage-controlled oscillator.KEYWORDS blind zone, charge pump (CP), dead zone, divider, loop filter, phase frequency detector (PFD), voltagecontrolled oscillator (VCO)

Section: Simulation Resultsmentioning

confidence: 99%

A faster phase frequency detector using transmission gate–based latch for the reduced response time of the PLL

2018

Circuit Theory & Apps

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“…In TSMC 180 nm process, the electron mobility is 2.3 times larger than hole mobility [17] . Therefore, for the channel resistances to be equilibrated, and for the inverters to switch at the mid-point of V DD , W p has to be by 2.3 times more than W n .…”

Section: When Both Mosfets Are Switching In the Saturation Regionmentioning

confidence: 95%

Frequency equation for the submicron CMOS ring oscillator using the first order characterization

2018

J. Semicond.

By utilizing the first order behavior of the device, an equation for the frequency of operation of the submicron CMOS ring oscillator is presented. A 5-stage ring oscillator is utilized as the initial design, with different Beta ratios, for the computation of the operating frequency. Later on, the circuit simulation is performed from 5-stage till 23-stage, with the range of oscillating frequency being 3.0817 and 0.6705 GHz respectively. It is noted that the output frequency is inversely proportional to the square of the device length, and when the value of Beta ratio is used as 2.3, a difference of 3.64% is observed on an average, in between the computed and the simulated values of frequency. As an outcome, the derived equation can be utilized, with the inclusion of an empirical constant in general, for arriving at the ring oscillator circuit’s output frequency.

“…As discussed earlier, when the outputs of the PFD are utilised in the CP, to turn the switches ON and OFF, the lagging or the leading state between the REF and DIV signals gets translated into source or sink current, which in turn is utilised by the loop filter to convert the same into a voltage waveform. The second order loop filter that is required for the generation of control voltage is designed as per the procedures that are discussed in [28]. The CP circuit is simulated as per the conventional design initially.…”

Section: Designs Of Cp and Vcomentioning

confidence: 99%

Integer‐ N charge pump phase locked loop for 2.4 GHz application with a novel design of phase frequency detector

IET Circuits, Devices & Systems

2020

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In this article, a novel design is presented, for an Integer-N charge pump phase locked loop (PLL). The design is with a resetless phase frequency detector, and with the differential design of charge pump. The voltage-controlled oscillator is of current starved type. The proposed PLL is not having any blind zone and is having near-zero dead zone. When compared to the conventional design, the current mismatch in the charge pump is reduced by 3.21%, and the lock time of the PLL is reduced by 79%. The PLL is intended for 2.4 GHz application, and the obtained lock time is 1.7 μs. The implementation is done with the three-stage ring oscillator, with divider of modulus as 24, in 180 nm TSMC technology. At 1.8 V supply voltage, the circuit consumes 9.72 mW of power.