Analysis of double-gate CMOS for double-pole four-throw RF switch design at 45-nm technology

Abstract

In this paper, we have analyzed a 45-nm RF CMOS switch design technology with the double-pole fourthrow circuit by using independently controlled double-gate MOSFET. The proposed switch reduces the number of transistors and increases the logic density per unit area as compare to the conventional CMOS switch. With the unique independent double-gate properties, we have demonstrated the potential advantages in terms of the drain current, threshold voltage, attenuation with ON resistance, flat-band capacitances, charge density and power dissipation of the proposed switch, which provides a switch with a significant drive circuit that is free from the signal propagation delay and additional voltage power supply. Moreover, the main emphasis is to provide a plurality of such switches arranged in a densely configured switch array, which provides a lesser attenuation, and better isolation with fast switching speed.

Measurement Process of MOSFET Device Parameters with VEE Pro Software for DP4T RF Switch

“…With the multiple antennas, data transfer rate is increased by the same factor as the numbers of antenna are used. Antenna selection system and switching mechanism is essential to circumvent the uses of several RF chain associated with the various antennas [8,9].…”

Characterization Process of MOSFET with Virtual Instrumentation for DP4T RF Switch – A Review

“…Few attempts have been made to build a scalable RF-MOSFET model, including the layout-based extrinsic elements. For RF MOSFET modeling, lots of issues need to be considered [14][15][16] especially the three most important parasitic components: gate resistance R g , which influences the input impedance and noise performance of RF-MOSFETs [17,18].…”