Analysis of electrical characteristics of polycrystalline silicon thin-film transistors under static and dynamic conditions

Valdinoci, M.; Colalongo, L.; Baccarani, G.; Pecora, A.; Policicchio, I.; Fortunato, G.; Plais, F.; Legagneux, Pierre; Reita, C.; Pribat, Didier

doi:10.1016/s0038-1101(97)00130-5

Cited by 37 publications

(14 citation statements)

References 9 publications

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“…where J n is the electron current density of an n-type device and the parameters A n and B n are the electron ionization coefficients; these values can be found in our previous publication [14] and are used widely to model impact ionization rate [16][17][18]. If device current can be designed to be far away from the highest electrical field region at a higher drain bias, a low IIR device, and a highly reliable TFT is achievable.…”

Section: Structure Simulation Device Measurement and Discussionmentioning

confidence: 99%

A Low Impact Ionization Rate Poly-Si TFT with a Current and Electric Field Split Design

et al. 2019

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In this study, a novel low impact ionization rate (low-IIR) poly-Si thin film transistor featuring a current and electric field split (CES) structure with bottom field plate (BFP) and partial thicker channel raised source/drain (RSD) designs is proposed and demonstrated. The bottom field plate design can allure the electron and alter the electron current path to evade the high electric field area and therefore reduce the device IIR and suppress the kink effect. A two-dimensional device simulator was applied to describe and compare the current path, electric field magnitude distributions, and IIR of the proposed structure and conventional devices. In addition, the advantages of a partial thicker channel RSD design are present, and the leakage current of CES-thin-film transistor (TFT) can be reduced and the ON/OFF current ratio be improved, owing to a smaller drain electric field.Keywords: polycrystalline silicon (poly-Si); thin-film transistor (TFT); current and electric field split (CES); kink effect; field plate (FP); raised source/drain (RSD)

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Section: Structure Simulation Device Measurement and Discussionmentioning

confidence: 99%

A Low Impact Ionization Rate Poly-Si TFT with a Current and Electric Field Split Design

et al. 2019

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“…In this regard, it is worth mentioning that quite different approaches have been proposed in the literature to address polysilicon-channel transistors. In the simplest case, polysilicon is treated under the effective medium approximation, i.e., by neglecting its granular nature and introducing a spatially uniform distribution of traps in the volume of the material [22][23][24][25]. This approach is assumed to be valid when the nonuniformities in device electrostatics arising from the localized nature of the traps at the grain boundaries are negligible.…”

Section: Introductionmentioning

confidence: 99%

A comparison of modeling approaches for current transport in polysilicon-channel nanowire and macaroni GAA MOSFETs

et al. 2020

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In this paper, we compare quantitatively the results obtained from the numerical simulation of current transport in polysilicon-channel MOSFETs under different modeling assumptions typically adopted to reproduce the basic physics of the devices, including the effective medium approximation and the description of polysilicon as the haphazard ensemble of monocrystalline silicon grains separated by highly defective grain boundaries. In the latter case, both pure drift-diffusion transport and a mix of intra-grain drift-diffusion and inter-grain thermionic emission are considered. Interest is focused on cylindrical nanowire and macaroni gate-all-around structures, due to their relevance in the field of 3-Dimensional NAND Flash memories, focusing not only on the average behavior but also on the variability in the electrical characteristics of the devices.

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“…Although simulations of poly-Si TFTs, some including photocurrent, have yielded a lot of information [6][7][8][9][10], up to now they have not led to design rules for the LDD structure.…”

Section: Introductionmentioning

confidence: 99%

Analysis of photocurrents in low‐temperature polysilicon thin‐film transistors and the use of simulation to design LDD devices

Nanno

Senda

Mashimo

et al. 2003

Electron Comm Jpn Pt II

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SUMMARYDesign rules are presented for the suppression of photocurrents generated in the depletion layers of the channel/drain junction regions of low-temperature poly-Si thin-film transistors (TFTs). Device simulation based on modeling the behavior of the density of states in a low-temperature poly-Si TFT was used to find the width of the junction depletion layer. These simulations show that in order to suppress photocurrents to below 6 pA, the LDD region must have a sheet resistance in the range of 30 and 70 kΩ/", which forces its length to exceed 1 µm.

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Analysis of electrical characteristics of polycrystalline silicon thin-film transistors under static and dynamic conditions

Cited by 37 publications

References 9 publications

A Low Impact Ionization Rate Poly-Si TFT with a Current and Electric Field Split Design

A Low Impact Ionization Rate Poly-Si TFT with a Current and Electric Field Split Design

A comparison of modeling approaches for current transport in polysilicon-channel nanowire and macaroni GAA MOSFETs

Analysis of photocurrents in low‐temperature polysilicon thin‐film transistors and the use of simulation to design LDD devices

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