Analysis of Error Recovery Schemes for Networks on Chips

Abstract

AS DEVICES SHRINK toward the nanometer scale, on-chip interconnects are becoming a critical bottleneck in meeting performance and power consumption requirements of chip designs. Industry and academia recognize the interconnect problem as an important design constraint, and, consequently, researchers have proposed packet-based on-chip communication networks, known as networks on chips (NoCs), to address the challenges of increasing interconnect complexity. [1][2][3][4][5] NoC designs promise to deliver fast, reliable, energy-efficient communication between on-chip components. Because most application traffic is bursty in nature, packet-switched networks are suitable for NoCs. 2,4,5 Another effect of shrinking feature size is that power supply voltage and device V t decrease, and wires become unreliable because they are increasingly susceptible to noise sources such as crosstalk, coupling noise, soft errors, and process variation.6 Using aggressive voltage-scaling techniques to reduce a system's power consumption further increases the system's susceptibility to various noise sources. Providing resilience from such transient delay and logic errors is critical for proper system operation.Error detection or correction mechanisms can protect the system from transient errors that occur in the communication subsystem. These schemes can use end-to-end flow control (network level) or switch-to-switch flow control (link level). In a simple retransmission scheme, the sender adds error detection codes (parity or cyclic redundancy check codes) to the original data, and the receiver checks the received data for correctness. If it detects an error, it requests the sender to retransmit the data. Alternatively, the sender can add error-correcting codes (such as Hamming codes) to the data, and the receiver can correct errors. Hybrid schemes with combined retransmission and error correction capabilities are also possible. Because the error detection/correction capability, area-power overhead, and performance of the various schemes differ, the choice of error recovery scheme for an application requires exploring multiple power-performance-reliability trade-offs.In this article, we relate these three major design constraints to characterize efficient error recovery mechanisms for the NoC design environment. We explore error control mechanisms at the data link and network layers and present the schemes' architectural details. We investigate the energy efficiency, error protection efficiency, and performance impact of various error recovery mechanisms.Our objective is twofold: First, we want to identify the major power overhead issues of various error recovery schemes, so that designers can create efficient mechanisms to address them. Second, we want to provide the Analysis of Error Recovery Schemes for Networks on ChipsEditor's note: Error resiliency is a must for NoCs, but it must not incur undue costsparticularly in terms of energy consumption. Here, the authors present an authoritative discussion of the trade-offs involved in va...

A Survey Addressing On-Chip Interconnect: Energy and Reliability Considerations

“…However, the large transceiver areas and wide multilayer wire paths these approaches use to achieve the required inductance and low resistance properties results in worse bit-rate per wire area figures of merit than simpler RC-mode signaling. However, at the architectural level a small number of global, lowlatency communication links, such as that proposed in [26] for network flow control or multicast signaling as proposed in [27] could be used to provide efficient automatic repeat request (ARQ) signaling in error detect and recover schemes, such as described using conventional signals in [5] and are deserving of further exploration.…”

“…Recent works have recognized that the reliability of on-chip interconnect circuits is quickly becoming a limiting design factor, with [5] pointing out that an interconnect BER of 10 −12 on a 16-node, 200 MHz NoC corresponds to a mean time to failure of just 26 minutes. This fact has motivated the exploration of techniques to improve system reliability absent the traditional means of applying additional timing margins.…”

“…This includes many of the error mitigation techniques reviewed in the previous section. Reference [5,44,45] take a different approach, applying error-correcting anddetecting codes to traditionally highly reliable full-swing interconnect circuits, thereby reducing the requirement to and impact of overdesigning voltage and timing margins on system performance and energy. To this effect, [44] explores the energy overhead of implementing a variety of errorcoding schemes on a 32-bit AMBA bus, and extends this evaluation to scaling bus voltages in [45].…”

“…To this effect, [44] explores the energy overhead of implementing a variety of errorcoding schemes on a 32-bit AMBA bus, and extends this evaluation to scaling bus voltages in [45]. Reference [5] examines the problem from the perspective of a network architect, evaluating the network overhead implications of implementing FEC and ARQ in a NoC environment. Here we extend these works by presenting a case study evaluating the overheads of applying similar error coding schemes to a custom, differential, low-swing interconnect circuit.…”

“…The result is inefficient overmargining of signal levels and timing, reduced yields and higher susceptibility to both static and transient errors being introduced to the system [4]. As such, both static manufacturing flaws and single-event-induced errors can unacceptably reduce the mean time to failure (MTTF) of traditionally robust circuits [5]. Taking steps to ensure the robustness and reliability of energy-efficient interconnect circuits should therefore be a design priority in order for energyefficient interconnect circuits to be considered a viable design choice.…”