Analysis of one-step majority logic decoding under correlated data-dependent gate failures

Brkic, Srdan; Ivaniš, Predrag; Vasić, Bane

doi:10.1109/isit.2014.6875304

Cited by 15 publications

(13 citation statements)

References 12 publications

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“…The first attempt to use a more advanced coding scheme to ensure fault tolerance of storage systems made from unreliable components is due to Taylor [5] and Kuznetsov [6]. Fault-tolerant decoding and storage has attracted significant attention lately, and numerous approaches have been proposed which exploit the inherent redundancy of the existing decoders [7], [8], [9], [10]. In this paper we show that by two simple but key modifications -the rewinding schedule and more reliable gates for critical computationsthe decoder can be made tolerant for a wide range of the gate failure rates.…”

Section: Introductionmentioning

confidence: 99%

Error Errore Eicitur: A Stochastic Resonance Paradigm for Reliable Storage of Information on Unreliable Media

Ivaniš

Vasić

2016

IEEE Trans. Commun.

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Abstract-We give an architecture of a storage system consisting of a storage medium made of unreliable memory elements and an error correction circuit made of a combination of noisy and noiseless logic gates that is capable of retaining the stored information with lower probability of error than a storage system with a correction circuit made completely of noiseless logic gates. Our correction circuit is based on iterative decoding of low-density parity check codes, and uses the positive effect of errors in logic gates to correct errors in memory elements. In the spirit of Marcus Tullius Cicero's "Clavus clavo eicitur," ("one nail drives out another") the proposed storage system operates on the principle: "Error errore eicitur" -"one error drives out another." The randomness that is present in the logic gates makes these classes of decoders superior to their noiseless counterparts. Moreover, random perturbations do not require any additional computational resources as they are inherent to unreliable hardware itself. To utilize the benefits of logic gate failures, our correction circuit relies on two key novelties: a mixture of reliable and unreliable gates and decoder rewinding. We present a method based on absorbing Markov chains for the probability of error analysis, and explain how the randomness in the variable and check node update function helps a decoder to escape to local minima associated with trapping sets.

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Section: Introductionmentioning

confidence: 99%

Error Errore Eicitur: A Stochastic Resonance Paradigm for Reliable Storage of Information on Unreliable Media

Ivaniš

Vasić

2016

IEEE Trans. Commun.

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“…Such reliable gates in the final decision circuitry can be realized by using larger transistors, slowing down the clock or using higher voltage supply. Similar assumption was also used in other relevant literature [2], [7].…”

Section: A Ldpc Codes and Decoding Algorithmmentioning

confidence: 82%

“…In order to characterize the hardware unreliability phenomenon accurately, Brkic et al in [7] used a Markov chain timing error model, which has enabled them to analyze the behavior of one-step majority logic decoders. Timing errors in the context of the stochastic decoders have been considered recently by Perez-Andrade et al [11] who have shown an inherent tolerance to timing errors of these type of decoders.…”

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confidence: 99%

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On Fault Tolerance of the Gallager B Decoder Under Data-Dependent Gate Failures

et al. 2015

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In this letter, we characterize the effect of datadependent gate failures on the performance of the Gallager B decoder of low-density parity-check codes. We show that this type of failures makes the decoder dependent on a transmitted codeword, thus rendering inapplicable the traditional analysis tools such as density evolution and trapping sets. By using Monte Carlo simulations, we identify two operating regions: one in which hardware unreliability leads to significant performance degradation and another in which the performance loss is negligible. Based on these results, we propose a simple modification of the decoder that ensures its fault tolerance.

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“…Following this line of research we reviled an error-correction potential that noisy decoders have, which is not visible by the density evolution analysis under uncorrelated failures. In a series of articles we showed robustness of different errorcorrection techniques to timing errors -one-step majority logic decoders [23], Gallager B decoders [24], bit-flipping decoders [25], [26], as well as coded memory architectures [27]. In this paper we especially emphasize two major contributions: 1) discovered positive impact of timing errors to decoder's correction capability and 2) ability of noisy decoders to achieve arbitrary low error probability.…”

Section: Introductionmentioning

confidence: 85%

Hard-decision decoding of LDPC codes under timing errors: Overview and new results

Brkic

Ivaniš

Vasić

2017

2017 25th Telecommunication Forum (TELFOR)

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Abstract-This paper contains a survey on iterative decoders of low-density parity-check (LDPC) codes built form unreliable logic gates. We assume that hardware unreliability comes from supply voltage reduction, which cause probabilistic gate failures, called timing errors.We are able to demonstrate robustness of simple Gallager B decoder to timing errors, when applied on codes free of small trapping sets, as well as positive effects that timing errors have on the decoding of codes with contains small trapping sets. Furthermore, we show that concept of guaranteed error correction can be applied to the decoders made partially from unreliable components. In contrast to the decoding under uncorrelated gate failures, we prove that bit-flipping decoding under timing errors can achieve arbitrary low error probability. Consequently, we formulate condition sufficient that memory architecture, which employs bit-flipping decoder, preserved all stored information.

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Analysis of one-step majority logic decoding under correlated data-dependent gate failures

Cited by 15 publications

References 12 publications

Error Errore Eicitur: A Stochastic Resonance Paradigm for Reliable Storage of Information on Unreliable Media

Error Errore Eicitur: A Stochastic Resonance Paradigm for Reliable Storage of Information on Unreliable Media

On Fault Tolerance of the Gallager B Decoder Under Data-Dependent Gate Failures

Hard-decision decoding of LDPC codes under timing errors: Overview and new results

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