Analysis of Soft Error Mitigation Techniques for Register Files in IBM Cu-08 90nm Technology

Naseer, R.; Bhatti, Rashed Zafar; Draper, J.

doi:10.1109/mwscas.2006.382112

Cited by 27 publications

(16 citation statements)

References 9 publications

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“…In [4] and [9], a useful analysis relevant to reliability of the TMR technique and some various Hamming codes is presented. The comparative analyses provided in section 4 employs this analysis provided in [4,9].…”

Section: Related Workmentioning

confidence: 99%

“…Fig.1 depicts the relation between the technology size, supply voltage and Q crit (the minimum charge needed for a particle strike to result in an SEU). One can see that with decrease in the supply voltage and technology size, Q cirt lowers more and more that is, the sensitivity to soft errors increases [9][10].…”

Section: Introductionmentioning

confidence: 99%

“…The most prominent and widely used technique, employable for reliability enhancement in flip-flops, level sensitive latches and SRAM memories is triple modular redundancy (TMR) [3,9]. In this technique, each memory cell is triplicated and voted using a voter circuitry to mask one bit upset in one of the triplicated cells.…”

Section: Introductionmentioning

confidence: 99%

“…To protect register files and cache memories in a microprocessor architecture, several parity-based techniques are proposed [4,9,11]. Comparing with the TMR technique, these methods impose less area overhead while, they usually cause more delay [9,13].…”

Section: Introductionmentioning

confidence: 99%

“…Comparing with the TMR technique, these methods impose less area overhead while, they usually cause more delay [9,13].…”

Section: Introductionmentioning

confidence: 99%

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Design of a Radiation Hardened Register File for Highly Reliable Microprocessors

Rajaei

2016

IJEM

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In this paper, a powerful bit upset masking (PBUM) technique for design of a high reliable register file is proposed. This technique is based on the triple modular redundancy (TMR) technique with the key capability of double faulty bit masking in every triad of bits while the TMR structure, only masks one fault in a triad. We implemented a 64-bit register file comprised of 64 registers protected with the proposed PBUM technique on FPGA. Our simulation results reveal that, over the TMR and some Hamming code-based techniques, our design offers a very higher robustness against radiation induced soft errors. Also, the proposed PBUM technique imposes a lower delay than its counterparts at the expense of a little higher area overhead. To reduce the area overhead, an area-efficient strategy is suggested that balances the reliability improvement and the area overhead. We show that, our technique using this area-aware strategy still has the highest reliability among the other considered techniques.

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