Analysis of the performance of a micromechanical test structure to measure stress in thick electroplated metal films

Smith, S.; Brockie, N. L.; Murray, Joanne F.; Wilson, Christopher J.; Horsfall, Alton B.; Terry, Jonathan G.; Stevenson, J.T.M.; Mount, Andrew R.; Walton, A.J.

doi:10.1109/icmts.2010.5466852

Cited by 7 publications

(10 citation statements)

References 7 publications

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“…The test chip design has been previously replicated across a 200 mm wafer using an 8 μm thick photoresist layer to form the mould for wafer-scale electroplating. This chip design successfully characterised the wafer-scale process confirming the value of the test structures and the chip layout for process development [25,27]. Fig.…”

Section: Test Chip Design and Fabricationsupporting

confidence: 55%

“…The test structure architecture used in this work is shown in Fig. 1 [25,26] and consists of two expansion arms and a pointer arm of width (W=8 µm) underneath which a sacrificial layer has been removed. Depending on whether the arms are in compression or tensile the pointer arm rotates in a different direction.…”

Section: Test Chip Design and Fabricationmentioning

confidence: 99%

“…Depending on whether the arms are in compression or tensile the pointer arm rotates in a different direction. From Y =  the stress ( is proportional to strain (, which can be calculated from the angle of rotation (θ) using (ε = θ ΔY/L) as described in [25], where, ΔY is the arm separation and L= 850 µm is the designed arm length without stress. The rotating strain structure has been selected for the straightforward simple surface micromachining process, its small footprint and the availability of an automated procedure for measuring the angle of rotation (Note: in this paper we have reported the angle of rotation -reference [27] reports the procedure to determine the stress).…”

Section: Test Chip Design and Fabricationmentioning

confidence: 99%

“…Following photoresist patterning ( Fig. 2(c)) the Ref [25] provides more details of the test chip layout.…”

Section: Test Chip Design and Fabricationmentioning

confidence: 99%

See 3 more Smart Citations

The Use of Test Structures to Perform Chip Level Characterization Studies of Ni and NiFe Electrochemical Deposition

Murray

Perry

Terry

et al. 2017

IEEE Trans. Semicond. Manufact.

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This paper describes the first use of test structures designed to characterise the fundamental properties of nickel and nickel-iron alloy films deposited using electroplating. The structures are used to perform a chip-level investigation into the effects of electrolyte bath composition on the characteristics of deposited films. The advantage of this methodology is that each electrolyte change does not require the replacement of the large volume bath associated with wafer scale manufacturing investigations, thereby making the characterisation and optimisation of electroplating baths far less time consuming, and considerably more cost effective.

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Section: Test Chip Design and Fabricationsupporting

confidence: 55%

Section: Test Chip Design and Fabricationmentioning

confidence: 99%

Section: Test Chip Design and Fabricationmentioning

confidence: 99%

“…Following photoresist patterning ( Fig. 2(c)) the Ref [25] provides more details of the test chip layout.…”

Section: Test Chip Design and Fabricationmentioning

confidence: 99%

See 2 more Smart Citations

The Use of Test Structures to Perform Chip Level Characterization Studies of Ni and NiFe Electrochemical Deposition

Murray

Perry

Terry

et al. 2017

IEEE Trans. Semicond. Manufact.

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show abstract

“…Publications in MEMS technologies report the use of thermal expansion to cause deflection of a free-floating needle [1][2][3][4][5][6][7]. This can be used to measure the stress applied by neighboring (and connected) features.…”

Section: Introductionmentioning

confidence: 98%

Test structure to evaluate the impact of neighboring features on stress of metal interconnects

Smith

Shroff

2014

2014 International Conference on Microelectronic Test Structures (ICMTS)

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The stress-inducing effects of neighboring metal interconnect features were studied using novel stressmigration test structures with various layouts of perpendicular neighboring combs. The structures with narrow widths showed no change in stressmigration performance, with or without near-neighbor structures. However, structures built with wider lines showed up to 3X worse stressmigration performance when perpendicular combs were present nearby, essentially independent of the spacing to the combs. Thus, near neighbor metal features were shown to be capable of degrading SM performance in some lines. Keywords-stress; voiding; test structure I. ABSTRACTPublications in MEMS technologies report the use of thermal expansion to cause deflection of a free-floating needle [1][2][3][4][5][6][7]. This can be used to measure the stress applied by neighboring (and connected) features. Free-floating shapes don't exist in a typical CMOS technology but the stress applied by neighboring structures is still present. As stress can modulate the reliability of the interconnects [8-12], understanding the impact of any neighboring features is important.This study used a novel test structure to apply stress to a via chain using comb features that had no electrical connection. Measurements of resistance shift due to stress-induced voiding (SIV), also known as stressmigration (SM), were used as a metric for that stress. Neighboring combs with various layouts were investigated, in order to test the hypothesis that perpendicular "aggressor" metal lines would apply stress to the device under test (DUT), resulting in worse SM performance. Furthermore, the effect should decrease with the distance between the aggressor lines and the DUT. SM is generally determined by measuring the initial resistance of a DUT, baking it at an elevated temperature (e.g., 150-225°C) for a long time (e.g., 1000 hrs) with no current flow, and then measuring its resistance again. The shift in resistance is its SM performance. In such a high-temperature environment, vacancies in metal interconnects can migrate and accumulate at the regions of stress discontinuities (e.g., vias), resulting in higher resistance. Therefore, a lower resistance shift after baking indicates better SM robustness in the sample.

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A wafer mapping technique for residual stress in surface micromachined films

Schiavone

Murray

Smith

et al. 2016

J. Micromech. Microeng.

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Analysis of the performance of a micromechanical test structure to measure stress in thick electroplated metal films

Cited by 7 publications

References 7 publications

The Use of Test Structures to Perform Chip Level Characterization Studies of Ni and NiFe Electrochemical Deposition

The Use of Test Structures to Perform Chip Level Characterization Studies of Ni and NiFe Electrochemical Deposition

Test structure to evaluate the impact of neighboring features on stress of metal interconnects

A wafer mapping technique for residual stress in surface micromachined films

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